Flat Panel Display Interface Encoding for Lower-EMI Data Links
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Solution Overview
Problem
Contemporary interface systems for flat panel displays require high-frequency clocks to transmit data, leading to significant electromagnetic interference (EMI).
Innovation Solution
An interface system that includes a serializer to convert parallel data into a series, a transmission circuit with a decoder to convert two bits into three bits, a driver to control electric currents, a reception circuit with amplifiers and comparators to recover the data, and a deserializer to convert back to parallel data, minimizing EMI by reducing the clock frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is transmitted by one bit at a time using high-frequency clock, then data transmission speed is improved, but electromagnetic interference increases
Solution Approach 1:
The patent applies periodic action by using a lower-frequency clock to transmit multiple bits in a sequential manner over multiple clock cycles. Instead of transmitting one bit per clock cycle at high frequency, the system transmits multiple bits (e.g., 2 bits) sequentially using a lower-frequency clock, thereby reducing electromagnetic interference while maintaining effective data transmission throughput.
Solution Approach 2:
The patent segments the data transmission process into multiple sequential steps, where each bit is transmitted separately over multiple clock cycles. This segmentation allows the use of lower clock frequency and reduces the need for high-speed signaling, thereby minimizing electromagnetic interference generated during data transmission.
2Object-generated harmful factors
If multiple bits are transmitted per clock cycle to reduce clock frequency, then electromagnetic interference is reduced, but device complexity increases
Solution Approach 1:
The patent introduces intermediary components such as serializers and deserializers that convert parallel data into sequential data and vice versa. These intermediary devices enable multiple bits to be transmitted per clock cycle by breaking down the complex simultaneous transmission into manageable sequential operations, thereby reducing electromagnetic interference while managing system complexity through modular design.
Solution Approach 2:
The patent transitions from a single-dimensional approach (one bit per clock cycle) to a multi-dimensional approach by transmitting multiple bits simultaneously across different data lines. This dimensional expansion allows parallel data transmission using lower clock frequencies, reducing electromagnetic interference while the added complexity is managed through structured encoding and decoding mechanisms.
3Productivity
If high-frequency clock is used for data transmission, then data transmission efficiency is improved, but stability of transmission deteriorates
Solution Approach 1:
The patent employs periodic action by using a lower-frequency clock to transmit multiple bits sequentially over multiple clock cycles. This approach improves transmission stability by avoiding the high-frequency signal integrity issues and electromagnetic interference that plague single-bit-per-cycle transmission, while maintaining effective data throughput through multiple bits per cycle.
Solution Approach 2:
The patent incorporates feedback mechanisms in the form of acknowledgment signals and error detection/correction codes that allow the receiver to verify successful data reception and request retransmission if errors occur. This feedback system ensures stable and reliable data transmission even when using lower clock frequencies and sequential bit transmission.
Data Source
AI summary
An interface system capable of minimizing an electro magnetic interference. The interface system may be constructed with a serializer for receiving a first data and second data having a plurality of bits from an external device and sequentially outputting bits of the received first data and second data; a transmission circuit including a decoder for converting two bits supplied from the serializer into three bits, a driver for controlling a flow of electric currents to correspond to the three bits and a transmission resistor to which a voltage is applied to correspond to the flow of the electric currents; a reception circuit including a reception resistor for receiving a voltage supplied the transmission resistor, amplifiers for amplifying a voltage applied to both ends of the reception resistor, comparators for recovering the three bits and an encoder for recovering the two bits using the three bit by comparing the voltage supplied to the amplifiers; a deserializer for recovering the first data and the second data while sequentially storing the two bits supplied from the reception circuit; and stabilization circuits for controlling the transmission circuit.