Display Interface Oversampling for High-Speed Data Capture
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Solution Overview
Problem
The accurate detection and capture of high-speed, narrow pulses in digital data streams, such as those used in digital displays, is challenging due to their rapid transition times and the need for precise synchronization in analog and digital interfaces.
Innovation Solution
A display interface system that employs oversampling clocks to identify and invalidate subsampling strings in bit sample sequences, allowing for the multiplexing of valid bit sample phases from a delay path, thereby effectively capturing data from high-speed data streams.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high-speed data transmission is implemented with narrow pulses and rapid transition times, then data rate is improved, but detection accuracy deteriorates
Solution Approach 1:
The patent applies preliminary action by performing oversampling at multiple phases before data capture. The system takes multiple samples of each bit period at different phases (e.g., 0°, 120°, 240°) and stores them in delay elements. This preliminary sampling across multiple phases allows the system to later select the most accurate sample phase, compensating for the difficulty of detecting narrow high-speed pulses. The oversampling occurs before the actual data capture decision is made.
2Measurement precision
If oversampling is used to improve detection accuracy, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the sampling process into multiple discrete phases. Instead of continuously varying the sampling phase, the system uses distinct sampling phases (e.g., three phases spaced 120° apart) with dedicated delay elements for each phase. This segmentation allows the complex oversampling function to be implemented using separate, manageable components rather than a single complex continuous-phase sampler.
Solution Approach 2:
The patent uses delay elements as intermediaries between the oversampled signals and the data capture logic. Each sampled phase is stored in a delay element, which acts as an intermediary buffer. This allows the system to hold multiple phase samples and selectively transfer them to the data capture register based on which phase provides the most accurate detection, simplifying the control logic while maintaining precision.
3Reliability
If multiple sampling phases are used to capture valid data, then reliability is improved, but processing time increases
Solution Approach 1:
The patent applies preliminary action by pre-sampling all possible phases and storing them in delay elements before the data capture decision is needed. During steady-state operation, the system has already prepared multiple phase samples, so selecting the valid phase requires only checking subsampling conditions and transferring from pre-loaded delay elements, rather than performing time-consuming searches or repeated sampling during critical data capture windows.
Data Source
AI summary
Structures and methods are provided for capturing data from a data bit stream. They primarily generate successive bit sample sequences that each comprise N interleaved bit sample phases, identify subsampling strings formed of less than N consecutive bit samples with the same bit sample value, invalidate the bit sample phase of any bit sample that adjoins the strings, and then form data with successive bit sample phases that remain valid after the invalidating step. From more than one valid bit sample phases, they identify a preferred valid bit sample phase as one whose bit samples least often adjoin transitions from one bit sample value to a different bit sample value and then form the data with the preferred valid bit sample phase. Preferably, copies of the bit sample sequences are delayed along a delay path to facilitate the identifying and invalidating steps and subsequently, valid bit sample phases are multiplexed from the delay path.