Display Interface Device Staggered Clock Edge Transmission

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Solution Overview

Problem

Existing display interface technologies face challenges in increasing display information transmission efficiency and reducing power consumption and electromagnetic interference (EMI), primarily due to difficulties in adjusting internal clock timing caused by clock skew, leading to data loss and increased overhead in packet transmission units, and redundant clock edge transmission across multiple channels.

Innovation Solution

The display interface device and method involve transmitting clock edge information at different timings for each channel, using a reception part to detect and generate delay-compensated internal clock signals by performing logical operations on clock edges from neighboring channels, allowing for longer transmission units without data loss and reducing EMI by dispersing clock edges across multiple channels.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the transmission unit length is increased to improve transmission efficiency, then the overhead ratio increases and power consumption increases

Engineering Contradiction:
Improvetransmission efficiencyVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent changes the parameter of clock edge transmission timing by introducing a time offset between different channels. This allows longer transmission units to be used without proportionally increasing overhead, as clock edges are no longer transmitted simultaneously across all channels but are staggered in time, thereby reducing peak power consumption while maintaining higher transmission efficiency.

Inventive Principle:
Principle #35Parameter changes

2Ease of operation

If multiple channels transmit clock edge information at the same timing to synchronize data transmission, then transmission coordination is simplified but EMI increases

Engineering Contradiction:
Improvetransmission coordinationVSAvoidEMI
Core Design Contradiction:
Ease of operationVSObject-generated harmful factors

Solution Approach 1:

The patent applies periodic action by transmitting clock edge information in a staggered periodic manner across different channels rather than simultaneously. Each channel transmits its clock edges at offset intervals, which distributes the electromagnetic energy over time and reduces peak EMI while maintaining synchronization through the periodic structure of the offset timing.

Inventive Principle:
Principle #19Periodic action

3Stability of the object's composition

If clock edge information is transmitted simultaneously across multiple channels to maintain synchronization, then timing alignment is easier but clock skew problems worsen

Engineering Contradiction:
Improvetiming alignmentVSAvoiddata loss due to clock skew
Core Design Contradiction:
Stability of the object's compositionVSReliability

Solution Approach 1:

The patent applies preliminary action by pre-calculating and pre-setting time offsets for clock edge transmission on different channels. This preliminary timing adjustment compensates for expected clock skew effects before data transmission begins, ensuring that clock edges arrive at the receiver in a synchronized manner despite transmission delays, thereby preventing data loss while maintaining timing alignment.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10249258B2Display interface device and data transmission method thereof
Publication Date: 2019.04.02 LG DISPLAY CO LTD
  • US10249258B2 patent drawing
  • US10249258B2 patent drawing
  • US10249258B2 patent drawing

AI summary

The present disclosure relates to a display interface device which can increase display information transmission efficiency and reduce power consumption and EMI, in which a transmission part transmits clock edge information included in a data packet of each channel at a different timing from clock edge information included in data packets of other channels. A reception part detects a clock edge of each channel from the data packet transmitted through each channel, generates an internal clock signal of each channel, synchronized with the detected clock edge, corrects a delay of each channel depending on a result of a logical operation performed on a delayed clock edge of a channel and a clock edge of another channel to further generate an internal clock signal of each channel, and restores the display information from the data packet of each channel using the internal clock signal of each channel.