Non-Rectangular Display Layout With Split Gate Lines for VR Resolution
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Solution Overview
Problem
Existing display devices, particularly those used in VR goggles, face challenges in achieving high resolution and efficient layout due to their non-rectangular, irregularly shaped display regions, which complicate the arrangement of driver circuits and signal lines, leading to issues like increased resistance and misalignment during manufacturing.
Innovation Solution
The display device employs a substrate with an irregularly shaped display region surrounded by driver circuits, where gate lines are split into lower and upper layers, and signal lines are arranged to intersect these, with specific connections to reduce resistance and prevent misalignment, allowing for high-resolution and downsized designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If driver circuits and signal lines are arranged in conventional rectangular layouts, then manufacturing is simpler, but resolution and field of view are reduced for non-rectangular display regions
Solution Approach 1:
The gate lines are divided into multiple segments (first gate lines, second gate lines, third gate lines) that extend in different directions to match the non-rectangular display region shape. This segmentation allows the gate line driver circuit to control pixels along curved or irregular boundaries, achieving high resolution for circular or octagonal displays while maintaining manufacturability through systematic segmentation of the control lines.
Solution Approach 2:
The patent employs asymmetric arrangements of gate lines and signal lines that are specifically designed to match the non-rectangular geometry of the display region. The gate lines extend along curved paths or at different angles rather than uniform rectangular grids, and signal lines are routed asymmetrically to connect to the irregularly shaped pixel array, optimizing the field of view and resolution for VR applications.
2Shape
If gate lines are arranged to follow curved paths for circular displays, then field of view increases, but resistance increases and manufacturing precision decreases
Solution Approach 1:
The patent introduces multiple layers of gate lines (first gate lines in one direction, second gate lines in another direction, third gate lines in a third direction) to create a three-dimensional wiring structure. This multi-layer approach allows curved gate line paths to be achieved by combining straight line segments across different layers, reducing the resistance increase that would occur with single-layer curved paths while maintaining the circular or octagonal display shape.
3Productivity
If driver circuits are placed around the display region, then layout efficiency improves, but misalignment during manufacturing increases
Solution Approach 1:
The gate line driver circuit is positioned to extend along the curved or irregular boundary of the display region before the pixel array is fully defined. This preliminary positioning of the driver circuit establishes a reference framework that guides the subsequent formation of gate lines and signal lines, ensuring consistent alignment throughout the manufacturing process even for complex non-rectangular geometries.
Data Source
AI summary
A display device includes a substrate, a gate-line driver circuit, a signal-line driver circuit, a plurality of gate lines, and a plurality of image-signal lines. The substrate has a display region having a polygonal shape with n vertices and arranged with a plurality of pixels as well as a frame region surrounding the display region. The gate-line driver circuit and the signal-line driver circuit are located over the frame region. The plurality of gate lines extends from the gate-line driver circuit to the display region. The plurality of image-signal lines extends from the signal-line driver circuit to the display region and intersects the plurality of gate lines. Each of the plurality of pixels includes a transistor having a first gate electrode, a semiconductor film over the first gate electrode, and a second gate electrode over the semiconductor film. Other features are described in the specification in detail.