Multi-Transistor Display Layout for Leakage and Gray Level Control
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Solution Overview
Problem
The complexity of fabrication processes and sensitivity to chemical gases in display apparatuses using polycrystalline and oxide semiconductor layers lead to issues with leakage current and image reliability, particularly in low gray level regions requiring precise current control.
Innovation Solution
A display apparatus design featuring a substrate with multiple transistors, each with specific semiconductor and insulating layers, including oxide semiconductor layers, to improve transistor performance and reduce current stress, with additional insulating layers to control capacitance and threshold voltage changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If different semiconductor layers (polycrystalline and oxide semiconductor) are used to prevent leakage current and improve transistor performance, then leakage current blocking is improved, but fabrication process complexity increases
Solution Approach 1:
The patent merges the formation of polycrystalline semiconductor layers and oxide semiconductor layers into a single integrated fabrication process. The oxide semiconductor layer is formed using the same sputtering process as the polycrystalline semiconductor layer, with continuous gas flow transition from Ar to Ar+O2, eliminating the need for separate fabrication processes and reducing overall process complexity.
Solution Approach 2:
The sputtering apparatus is designed to perform multiple functions: forming both polycrystalline semiconductor layers and oxide semiconductor layers using the same equipment and process chamber. The gas delivery system can universally deliver different gas compositions (Ar, Ar+O2, Ar+N2) to the substrate, allowing a single apparatus to handle diverse semiconductor material deposition requirements.
2Reliability
If oxide semiconductor layer is used to improve leakage current blocking, then leakage current is reduced, but sensitivity to chemical gases and fabrication process complexity increases
Solution Approach 1:
The patent changes the gas composition parameter during the sputtering process to control the semiconductor layer properties. By transitioning from pure Ar gas to Ar+O2 mixed gas, the process forms oxide semiconductor layers with desired electrical characteristics. This parameter change allows precise control over the semiconductor layer's oxidation state and electrical properties, reducing sensitivity to chemical gas variations.
3Reliability
If thin film transistor with oxide semiconductor layer is used, then leakage current blocking is improved, but threshold voltage changes more sensitively affecting image quality
Solution Approach 1:
The patent implements a feedback mechanism where the gas flow rate and composition are dynamically adjusted based on the desired threshold voltage characteristics. By monitoring and controlling the Ar+O2 gas mixture ratio during sputtering, the process optimizes the oxide semiconductor layer formation to achieve stable threshold voltage, compensating for the inherent sensitivity of oxide semiconductors to threshold voltage changes.
4Reliability
If oxide semiconductor layer is used to improve leakage current blocking, then current control is improved, but current change rate with respect to voltage change increases deteriorating low gray level regions
Solution Approach 1:
The patent optimizes the gas composition parameters (Ar+O2 ratio) during oxide semiconductor layer formation to control the material's electrical characteristics. By adjusting the oxygen content in the sputtering gas, the process fine-tunes the semiconductor layer's carrier concentration and mobility, thereby controlling the current-voltage characteristics to reduce the current change rate and improve low gray level display precision.
Data Source
AI summary
A display apparatus includes a substrate having a display area and a non-display area; a first transistor including a first semiconductor layer on the substrate, a first insulating layer on the first semiconductor layer, a first gate electrode on the first insulating layer and a second insulating layer on the first gate electrode, a second transistor including a second semiconductor layer on the substrate and a second gate electrode on the first insulating layer, and a third transistor including a third semiconductor layer on the substrate and a third gate electrode on the second insulating layer