Display Device Leakage Current Reduction via Stacked Transistors
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Solution Overview
Problem
Existing display devices with double-gate transistors face challenges in precise control due to limited transistor count and complex wiring, making it difficult to achieve stable operation in small regions.
Innovation Solution
The display device incorporates a semiconductor layer, gate insulating film, and multiple interlayer insulating films stacked on a substrate, with scanning signal lines, constant potential wires, and data signal lines arranged in a specific configuration to include multiple transistors and reduce leakage current, featuring an overlap connector between data signal lines and constant potential wires to stabilize transistor operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If more transistors are added to increase control precision, then control precision is improved, but device complexity and wiring complexity increase
Solution Approach 1:
The patent utilizes the vertical dimension by stacking multiple display wires (first, second, and third display wires) at different heights through interlayer insulating films. This allows multiple transistors to be integrated in a compact region without increasing planar wiring complexity, as the additional transistors are arranged in the vertical dimension rather than expanding the 2D layout.
Solution Approach 2:
The patent embeds multiple transistors within a nested structure where the first, second, and third display wires are stacked within the same pixel circuit region. The transistors are formed using these stacked wires as gate electrodes, allowing multiple control elements to be nested within a single pixel circuit area, thereby increasing control precision without proportionally increasing overall device complexity.
2Reliability
If more transistors are added to reduce leakage current, then reliability is improved, but manufacturing complexity increases
Solution Approach 1:
The patent divides the pixel circuit into multiple segments by incorporating first, second, and third transistors with distinct gate electrodes formed from the stacked display wires. Each transistor can be independently controlled and manufactured, allowing the leakage current to be reduced through segmented control while maintaining manageable manufacturing complexity through modular transistor design.
Solution Approach 2:
By forming multiple transistors using the vertically stacked display wires as gate electrodes, the patent achieves enhanced reliability through increased transistor count without proportionally increasing manufacturing complexity. The vertical stacking allows multiple transistors to be formed in the same manufacturing process step, simplifying production compared to adding transistors in the planar dimension.
3Area of stationary object
If transistors are arranged in a compact region, then area is reduced, but wiring layout design becomes more difficult
Solution Approach 1:
The patent resolves the layout design difficulty by utilizing the vertical dimension to stack multiple display wires and transistors within the same pixel circuit area. This allows compact arrangement of multiple transistors without requiring complex 2D wiring layouts, as the vertical stacking provides natural separation and routing paths for the wiring.
Solution Approach 2:
The patent segments the wiring structure into multiple distinct layers (first, second, and third display wires) that can be independently routed and positioned. This segmentation simplifies layout design by allowing each wire layer to be optimized separately, reducing the overall design complexity while maintaining compact pixel circuit area.
Data Source
AI summary
A display device includes: a semiconductor layer; a gate insulating film; a first display wire; a first interlayer insulating film; a second display wire; a second interlayer insulating film; and a third display wire stacked on a substrate in this order, pixel circuits being provided corresponding to intersections of data signal lines and scanning signal lines included in the third display wire, each of the pixel circuits including a first transistor and a second transistor in which any one of the scanning signal lines overlaps the semiconductor layer through the gate insulating film, one terminal of the first transistor and one terminal of the second transistor are connected together through a connector included in a conductor region of the semiconductor layer, and the connector includes an overlap connector overlapped in a plan view with the data signal lines through a constant potential wires included in the first display wire.