Display Level Shifter With Shared Memory Channel Selection
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Solution Overview
Problem
Existing level shifters in display devices require multiple memories and output buffers for each channel, increasing cost and size.
Innovation Solution
A level shifter design that includes a logic circuit to generate edge signals at defined time points and a channel selection circuit to selectively output these signals to multiple channels, reducing the need for individual memories and output buffers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a memory and output buffer are disposed for each channel in conventional level shifters, then channel signal processing capability is ensured, but device size and manufacturing cost increase
Solution Approach 1:
The patent merges the memory and output buffer resources across multiple channels by implementing a shared memory structure that stores timing data for all channels and a single output buffer that sequentially serves multiple channels through time-division multiplexing. This eliminates the need for separate memory and buffer components for each channel, directly reducing device size while maintaining signal processing capability.
Solution Approach 2:
The patent creates universal components that serve multiple functions: the shared memory stores timing data for all channels simultaneously, and the single output buffer functions as the output buffer for all channels through selective activation based on channel identification signals. This multi-functionality allows one component to replace what would traditionally require multiple dedicated components.
2Reliability
If a memory and output buffer are disposed for each channel in conventional level shifters, then channel signal processing capability is ensured, but manufacturing cost increases
Solution Approach 1:
The patent merges the memory and output buffer resources across multiple channels by implementing a shared memory structure that stores timing data for all channels and a single output buffer that sequentially serves multiple channels through time-division multiplexing. This eliminates the need for separate memory and buffer components for each channel, directly reducing device size while maintaining signal processing capability.
Solution Approach 2:
The patent creates universal components that serve multiple functions: the shared memory stores timing data for all channels simultaneously, and the single output buffer functions as the output buffer for all channels through selective activation based on channel identification signals. This multi-functionality allows one component to replace what would traditionally require multiple dedicated components.
3Area of stationary object
If timing data is stored for multiple channels in a shared memory, then device size is reduced, but timing precision for multiple channels must be maintained
Solution Approach 1:
The patent segments the timing data storage within the shared memory by organizing timing data for different channels into distinct, separately addressable memory locations. Each channel's timing parameters (such as rising edge timing, falling edge timing, and pulse width) are stored in dedicated memory cells that can be independently accessed and modified, ensuring that timing precision for each channel is maintained despite sharing the same physical memory resource.
Solution Approach 2:
The patent implements feedback mechanisms where the controller reads back stored timing data to verify accuracy, and adjusts timing parameters based on detected edge positions in the input signal. This closed-loop approach ensures that timing precision is maintained by continuously monitoring and correcting timing data stored in the shared memory.
Data Source
AI summary
Embodiments disclose a level shifter including a logic unit configured to receive timing data and channel data and output an edge signal and a channel signal at a time point defined in the timing data, and a channel selection unit configured to select at least one channel from among a plurality of connected channels according to the channel signal and transmit the edge signal, and a display device including the same.