Display Level Shifter Gating During Timing Controller Reset

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional level shifters in display devices output abnormal signals during the initial stage of operation when the timing controller is in a floating state, leading to malfunctions due to the fixed enable level of the output enable signal, which causes glitches and improper level shifting.

Innovation Solution

The display device incorporates an output enable signal control part that synchronizes the output enable signal with the reset signal to control the level shifter's operation, disabling it during the switching period to prevent abnormal signal output and enabling it only after the reset signal is applied, thereby preventing malfunctions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the output enable signal is fixed at enable level to keep the level shifter always available, then the level shifter can continuously process timing control signals, but abnormal signals are level-shifted during the floating state causing glitches and malfunctions

Engineering Contradiction:
Improvecontinuous signal processing capabilityVSAvoidsignal stability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The output enable signal is changed from a fixed state to a dynamic state that transitions between enable and disable levels based on the reset signal timing. This allows the level shifter to adapt its operational state, being disabled during the floating period and enabled during normal operation, thus preventing abnormal signal processing while maintaining continuous processing capability during stable operation

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The reset signal is introduced as an intermediary control signal that mediates between the power supply voltage application and the level shifter operation. By using the reset signal timing as a reference, the output enable signal control part can coordinate the level shifter's enable/disable state, preventing abnormal signals from being processed while maintaining normal operation after initialization

Inventive Principle:
Principle #24Intermediary (Mediator)

2Loss of time

If the level shifter is enabled during the switching period to process signals immediately, then signal processing latency is reduced, but abnormal signals from the floating state are output causing display malfunctions

Engineering Contradiction:
Improvesignal processing latencyVSAvoidabnormal signal output
Core Design Contradiction:
Loss of timeVSObject-affected harmful factors

Solution Approach 1:

The output enable signal is disabled in advance during the switching period before normal operation begins. This preliminary disabling prevents abnormal signals from being processed during the floating state, and only after the reset signal is applied (indicating stable operation) does the level shifter become enabled, thus eliminating the harmful effect of abnormal signal output

Inventive Principle:
Principle #9Preliminary anti-action

Solution Approach 2:

The system performs a preliminary initialization phase where the output enable signal is kept disabled during the switching period. This preliminary action prepares the system by preventing abnormal signal processing, and only after this initialization is complete (when reset signal is applied) does normal signal processing begin, ensuring no harmful signals are output

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentEP3174040B1Display device and driving method thereof
Publication Date: 2024.03.20 LG DISPLAY CO LTD
  • EP3174040B1 patent drawingFigure 1
  • EP3174040B1 patent drawingFigure 2
  • EP3174040B1 patent drawingFigure 3~4

AI summary

A display device comprises: a timing controller that is turned on to a floating state by a first logic voltage and, after a switching period, switches from the floating state to a normal operating state by a reset signal to generate timing control signals; a level shifter that receives the first logic voltage and a second logic voltage and level-shifts the timing control signals to the second logic voltage and outputs the same; and an output enable signal control part that outputs an output enable signal at enable level LOW or disable level HIGH, in synchronization with the reset signal, wherein, during the switching period, the level shifter receives the output enable signal at disable level HIGH and stops level shifting.