Display Interconnection Layout for Light Extraction and Mura Control
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Solution Overview
Problem
The existing methods for manufacturing display devices face challenges in achieving high light extraction rates, which is crucial for large-scale display devices, as they often result in poor light extraction efficiency.
Innovation Solution
The proposed solution involves a display device structure that includes a substrate with an active region and a border region, featuring a first and second interconnection metal layer, passivation layers, through vias, electrodes, and bonding pads, which are strategically formed to improve light extraction and balance stresses across the active and border regions, thereby enhancing light emission efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Illumination intensity
If conventional manufacturing methods are used for display devices, then the manufacturing process is simple, but the light extraction rate is poor
Solution Approach 1:
The patent divides the manufacturing process into distinct segments: forming interconnection metal layers in both active and border regions, selectively removing metal layers in specific regions, and forming through vias at controlled depths. This segmentation allows optimization of light extraction in the active region while maintaining structural integrity in the border region, resolving the contradiction between improved light extraction and manufacturing complexity.
Solution Approach 2:
The patent applies different structures to different regions: the active region receives optimized through via structures with specific depths and metal layer configurations to maximize light extraction, while the border region maintains a different configuration for structural support. This local differentiation enables high light extraction rates without requiring complex modifications across the entire device.
2Stability of the object's composition
If interconnection metal layers are formed in both active and border regions, then stress balance is improved, but manufacturing complexity increases
Solution Approach 1:
The patent selectively removes (extracts) the interconnection metal layer from the border region after initially forming it across the entire substrate. This extraction approach allows the metal layer to provide stress balance during manufacturing, then be removed in the border region to simplify the final structure and reduce manufacturing complexity for subsequent steps.
Solution Approach 2:
The interconnection metal layer is formed in both active and border regions as a preliminary step to establish stress balance during the manufacturing process. This preliminary action ensures structural stability during fabrication, after which selective removal in the border region occurs to achieve the final optimized structure.
3Reliability
If through vias are formed to connect interconnection metal layers, then electrical connection is improved, but light extraction efficiency decreases
Solution Approach 1:
The patent forms through vias with controlled depth that partially penetrate the passivation layer rather than completely through. This partial action provides sufficient electrical connection reliability for the interconnection metal layers while minimizing the impact on light extraction efficiency, as the via depth is optimized to balance both requirements.
Solution Approach 2:
The patent optimizes the depth parameter of the through vias to achieve the right balance between electrical connection and light extraction. By carefully controlling the via depth to penetrate only partially through the passivation layer, the system achieves reliable electrical connectivity while maintaining high light extraction efficiency.
Data Source
AI summary
The disclosure provides a display device including a substrate, a first interconnection metal layer, a second interconnection metal layer, a passivation layer, a first through via, a second through via, a first electrode and a bonding pad. The substrate includes active and border regions. The first interconnection metal layer is disposed on the substrate and located in the active region. The second interconnection metal layer is disposed on the substrate and located in the border region. The passivation layer is disposed on the first and second interconnection metal layers. The first through via passes through the passivation layer and is electrically connected to the first interconnection metal layer. The second through via passes through the passivation layer and is electrically connected to the second interconnection metal layer. The first electrode is disposed on the first through via. The bonding pad is disposed on the second through via.