Display Line Layer Layout for Narrow Bezels and Low Capacitance
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Solution Overview
Problem
Display devices face challenges in minimizing the bezel area and reducing parasitic capacitance between lines, which affects design flexibility and image quality.
Innovation Solution
The display device incorporates a connection member in a different layer from the connected line, connected via a via-electrode, and optimizes the arrangement of lines in the non-display area to minimize bezel size and parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If lines are arranged in the non-display area to connect display area components, then electrical connection is achieved, but parasitic capacitance increases between adjacent lines
Solution Approach 1:
The patent transitions from planar arrangement to three-dimensional stacking by placing different lines in different layers (first line layer and second line layer separated by insulating layers). This vertical dimensionality allows lines to be electrically connected while minimizing horizontal overlap, thereby reducing parasitic capacitance between adjacent lines in the non-display area.
2Area of stationary object
If bezel area is minimized to achieve wide display area, then display area ratio increases, but design freedom and electrical routing become more difficult
Solution Approach 1:
By utilizing multiple layers for line arrangement, the patent achieves compact bezel area while maintaining design flexibility. The first line layer and second line layer can be independently routed and connected via via-electrodes, allowing various electrical connection configurations within a minimized bezel boundary.
Solution Approach 2:
The via-electrode acts as an intermediary element connecting lines across different layers. This mediator enables electrical connection between the first line layer and second line layer without requiring direct contact, thus maintaining design freedom while achieving compact bezel configuration.
3Ease of manufacture
If connection member is placed in the same layer as the line, then manufacturing is simpler, but parasitic capacitance and electrical interference increase
Solution Approach 1:
The connection member is positioned in a different layer (third line layer) than the connected line (first or second line layer), separated by insulating layers. This vertical separation reduces parasitic capacitance and electrical interference while the via-electrode provides a controlled electrical connection path, balancing manufacturing complexity with performance requirements.
Data Source
AI summary
A display device includes an opening area formed in a display area and a non-display area surrounding the opening area, wherein the display area includes a plurality of pixels and a plurality of lines connected to the plurality of pixels, the non-display area includes a connection member connected to at least one of the plurality of lines of the display area, and the connection member is disposed in a different layer from the connected line and is electrically connected to the line by a via-electrode.