Display Panel Line Layout to Reduce Scan-Data Short Circuits

The patent applies dimensionality change by routing scan lines and data lines in different layers (third substrate layer and first substrate layer respectively), transforming a two-dimensional intersection problem into a three-dimensional non-intersecting layout. This allows lines to cross in space without actual contact, reducing short circuit risk while maintaining standard pixel arrangement.

The patent segments the conductive lines into multiple sections with insulating layers positioned between segments. By dividing the continuous scan lines and data lines into discrete segments separated by insulating structures, the patent eliminates direct intersection points where short circuits could occur, while still achieving the necessary electrical connections at pixel locations.

The patent utilizes vertical layering to reduce horizontal intersections. By assigning scan lines to the third substrate layer and data lines to the first substrate layer, the design eliminates the need for numerous two-dimensional intersections while maintaining full connectivity. This dimensional approach simplifies the manufacturing process by reducing particle contamination risks at intersection points.

The patent introduces insulating layers and contact holes as intermediary structures between scan lines and data lines. These intermediaries enable electrical connections without direct line contact, allowing the layout to avoid complex intersection management while maintaining functional connectivity. The insulating layers act as mediators that prevent short circuits while enabling controlled signal transmission.