Display Signal Line Segmentation to Reduce Boundary Stripe Artifacts
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Solution Overview
Problem
Increasing screen size and definition in display devices leads to higher wiring resistance and parasitic capacitance, causing signal delay, waveform distortion, and increased power consumption, resulting in deteriorated display quality and unevenness.
Innovation Solution
The display device is designed with signal lines divided into upstream and downstream segments, each connected to separate driver circuits, reducing wiring resistance and parasitic capacitance by half, and employing amorphous or crystalline semiconductors for transistors to enhance display quality and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If screen size and definition are increased, then display quality and resolution are improved, but wiring resistance increases causing signal delay and power consumption increase
Solution Approach 1:
The signal lines are divided into multiple segments with intermediate buffer circuits or driver circuits positioned at strategic locations. This segmentation reduces the effective length of each wiring segment, thereby reducing wiring resistance and power consumption while maintaining overall display quality.
2Measurement precision
If screen size and definition are increased, then display quality and resolution are improved, but signal transmission is delayed due to increased wiring resistance
Solution Approach 1:
The signal lines are divided into multiple segments with intermediate buffer circuits or driver circuits positioned at strategic locations. This segmentation reduces the effective length of each wiring segment, thereby reducing signal transmission delay while maintaining overall display quality.
3Measurement precision
If screen size and definition are increased, then display quality is improved, but parasitic capacitance increases causing waveform distortion
Solution Approach 1:
The signal lines are divided into multiple segments with intermediate buffer circuits or driver circuits positioned at strategic locations. This segmentation reduces the effective length of each wiring segment, thereby reducing parasitic capacitance and minimizing waveform distortion while maintaining overall display quality.
4Loss of energy
If wiring resistance is reduced by using copper, then power consumption is reduced, but manufacturing complexity increases
Solution Approach 1:
The signal lines are divided into multiple segments with intermediate buffer circuits or driver circuits positioned at strategic locations. This segmentation reduces the effective length of each wiring segment, thereby reducing wiring resistance and power consumption while avoiding the need for copper wiring and associated manufacturing complexity.
Data Source
AI summary
A display device with favorable display quality is provided. A display portion where a plurality of pixels is arranged in a matrix is divided into Region A and Region B, i.e., regions on the upstream side and the downstream side of a scanning direction. A signal line for supplying an image signal is provided in each of Region A and Region B. Region A and Region B adjoin each other such that a boundary line showing the boundary between the regions is bent. Bending the boundary line suppresses formation of a stripe in a boundary portion. For example, in a given column, the total number of pixels electrically connected to a signal line in Region A is made different from the total number of pixels electrically connected to a signal line in Region B.