Display Signal Line Shielding Layout for High-Resolution Panels

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Solution Overview

Problem

Existing display devices face challenges in increasing resolution without deteriorating image quality, as higher pixel density requires more integrated signal lines, leading to potential coupling and interference issues.

Innovation Solution

A display device design featuring a specific layering and connection structure of semiconductor layers, insulating layers, and signal lines, including shielding electrodes and connecting members, which reduces coupling and interference between signal lines.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If more pixels are arranged in a limited area to increase resolution, then image clarity and vividness are improved, but signal line coupling and interference increase causing image quality deterioration

Engineering Contradiction:
ImproveresolutionVSAvoidsignal line coupling and interference
Core Design Contradiction:
Measurement precisionVSObject-affected harmful factors

Solution Approach 1:

A shielding electrode is introduced as an intermediary element between signal lines to block electromagnetic coupling and interference. The shielding electrode is electrically connected to a reference potential (ground or power supply line) and positioned to intercept coupling between adjacent signal lines, thereby preventing harmful electromagnetic interference while maintaining high pixel density for high resolution display.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Measurement precision

If more pixels are arranged in a limited area to increase resolution, then image clarity is improved, but device complexity increases due to more integrated signal lines

Engineering Contradiction:
ImproveresolutionVSAvoidsignal line integration
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The shielding structure is added in the vertical dimension (z-direction) rather than increasing horizontal signal line separation. By stacking the shielding electrode above or below the signal lines and connecting it to reference potential, the solution addresses interference issues through dimensional extension without increasing planar complexity of signal line routing.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Reliability

If shielding structures are added to reduce signal line coupling, then image quality is maintained, but device complexity and manufacturing difficulty increase

Engineering Contradiction:
Improveimage qualityVSAvoidlayer structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The shielding electrode is integrated with existing reference potential structures (ground lines or power supply lines) already present in the display device. Rather than creating entirely separate shielding structures, the solution repurposes existing conductive layers as shielding elements, thereby maintaining image quality while minimizing additional device complexity and manufacturing steps.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20260068466A1Display device
Publication Date: 2026.03.05 SAMSUNG DISPLAY CO LTD
  • US20260068466A1 patent drawing
  • US20260068466A1 patent drawing
  • US20260068466A1 patent drawing

AI summary

A display device includes a first semiconductor layer disposed on a substrate; a first insulating layer disposed on the first semiconductor layer; a scan line disposed on the first insulating layer; a second insulating layer on the scan line; an inverted scan line on the second insulating layer; a third insulating layer disposed on the inverted scan line; a second semiconductor layer disposed on the third insulating layer; a fourth insulating layer disposed on the second semiconductor layer; an initializing voltage line disposed on the fourth insulating layer and overlapping the scan line; a first transistor including a channel disposed in the first semiconductor layer and receiving a gate signal through the scan line; and a second transistor including a channel disposed in the second semiconductor layer and receiving a gate signal through the inverted scan line.