Link Line Layering for Display Parasitic Capacitance
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Solution Overview
Problem
Parasitic capacitance between signal lines in display devices affects the performance by causing imbalance in sensed values of driving transistors, leading to reduced image quality and increased power consumption.
Innovation Solution
The display device incorporates a link unit with reduced parasitic capacitance by disposing the second link line on a layer different from the first link line and changing its structure to a whole electrode structure, thereby minimizing differences in parasitic capacitance across sub-pixels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If data lines and driving voltage lines are disposed close to each other in the active area, then the display device can achieve high resolution and compact design, but parasitic capacitance between the lines increases affecting performance
Solution Approach 1:
The patent moves the second link line from the same plane as the first link lines to a different layer (upper or lower layer) in the non-active area. This spatial reconfiguration in the vertical dimension reduces the parasitic capacitance between data lines and driving voltage lines while maintaining compact horizontal layout in the active area.
Solution Approach 2:
The patent divides the link lines into two groups: first link lines extending from data lines in the active area, and a second link line disposed on a different layer in the non-active area. This segmentation separates the signal paths to minimize parasitic coupling while maintaining electrical connectivity.
2Ease of manufacture
If conventional link line structures are used, then the manufacturing process is simple, but differences in parasitic capacitance across sub-pixels cause imbalance in sensed values of driving transistors
Solution Approach 1:
By disposing the second link line on a different layer from the first link lines, the patent creates vertical separation that reduces parasitic capacitance variations across different sub-pixels. This layered approach maintains manufacturing simplicity while achieving uniform parasitic capacitance characteristics.
Solution Approach 2:
The patent configures the link lines to achieve equipotential distribution by reducing parasitic capacitance differences across sub-pixels. The second link line on a different layer helps equalize the electrical environment for all sub-pixels, eliminating sensed value imbalance in driving transistors.
3Device complexity
If link lines are disposed in the non-active area on the same layer, then the structure is simple, but parasitic capacitance between first link lines and second link line affects display performance
Solution Approach 1:
The patent resolves the parasitic capacitance issue between link lines by disposing the second link line on a different layer from the first link lines in the non-active area. This vertical separation in the layer dimension reduces parasitic coupling while maintaining a relatively simple overall configuration.
Data Source
AI summary
A display device can include a display panel having an active area and a non-active area, a plurality of data lines and driving voltage lines disposed in the active area, a plurality of first link lines disposed in the non-active area and respectively connected to the plurality of data lines, and one second link line disposed over the plurality of first link lines and connected to a part of the plurality of driving voltage lines. As a result, quality of the display panel can be improved, and a total resistance of the driving voltage lines can be reduced, so that power consumption of the display panel can be reduced.