Flat Display Link Lines Minimize Resistance Variation
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Solution Overview
Problem
Existing flat display devices with dual link structures experience significant resistance variation between adjacent link lines due to process variations, leading to poor picture quality, especially when trying to minimize bezel width.
Innovation Solution
Implementing a dual link structure with alternating layers for each link line, where each link line consists of a first metal line on a lower layer and a second metal line on an upper layer, connected by a contact portion, and adjusting the lengths and cross-sectional areas of these metal lines to maintain consistent resistance across adjacent lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a dual link structure is applied with adjacent gate link lines formed on different layers to reduce bezel width, then the bezel area width is reduced, but resistance variation between adjacent link lines increases due to process variations in thickness and line width
Solution Approach 1:
The patent applies different structural configurations to different link lines based on their layer position. Odd-numbered link lines use a first configuration while even-numbered link lines use a second configuration, allowing local optimization to compensate for process variations and achieve uniform resistance across all link lines
Solution Approach 2:
The patent modifies geometric parameters (line width, thickness, length) of the link lines formed on different layers to compensate for process variations. By adjusting these parameters, the resistance of link lines on different layers is equalized, resolving the resistance variation issue while maintaining the narrow bezel design
2Length of moving object
If odd numbered gate link lines are formed as gate line metals at a first layer and even numbered gate link lines at a second layer, then the width between link lines is reduced enabling narrow bezel design, but picture quality deteriorates due to great resistance variation affecting scan signal transmission
Solution Approach 1:
The patent implements different structural configurations for odd and even numbered link lines based on their layer position. This local differentiation allows compensation for process variations specific to each layer, ensuring uniform resistance and reliable scan signal transmission across all link lines
Solution Approach 2:
The patent introduces asymmetric structural configurations where odd-numbered link lines and even-numbered link lines have different geometries (line width, thickness, or length). This asymmetry is deliberately designed to compensate for systematic process variations between layers, achieving uniform electrical characteristics despite the asymmetric physical structure
Data Source
AI summary
The present invention relates to a flat display device and method of fabricating the same which can make narrow bezel design easy and minimize resistance variation between adjacent link lines for improving of a picture quality. The flat display device includes a display region having a plurality of pixels, a driving integrated circuit for forwarding driving signals for driving the plurality of pixels, and a plurality of link lines for transmitting the driving signals to the display region, wherein each of the plurality of link lines includes a first metal line, a second metal line formed on a layer different from the first metal line, and a contact portion for connecting the first and second metal lines to each other.