Display Data Line Load Layout for Capacitance and Static Control
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Solution Overview
Problem
Defects occur in the manufacturing process of display apparatuses, particularly due to issues with parasitic capacitance and static electricity affecting data lines, leading to inconsistencies in pixel luminance and potential short circuits.
Innovation Solution
The display apparatus is designed with specific load configurations, including 1-1st and 1-2nd lower loads and 1-1st and 1-2nd upper loads, which are insulated and spaced apart to equalize capacitance and minimize charge accumulation, reducing defects during manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If data lines are extended into the peripheral area for manufacturing control, then manufacturing precision is improved, but parasitic capacitance increases causing pixel luminance inconsistency
Solution Approach 1:
The patent converts the harmful parasitic capacitance into a beneficial element by introducing compensation circuits that utilize the capacitance value for calibration purposes. The extended data lines are equipped with test structures and measurement circuits that allow the manufacturing system to measure and compensate for the parasitic capacitance, thereby transforming the previously harmful effect into a controllable parameter for achieving uniform pixel luminance.
Solution Approach 2:
The patent changes the electrical parameters of the data lines by introducing adjustable compensation elements (such as variable capacitors or resistors) that can be tuned to offset the parasitic capacitance. By modifying the circuit parameters through calibration during manufacturing, the system achieves consistent luminance across all pixels despite the presence of extended data lines with inherent parasitic capacitance.
2Device complexity
If load elements are placed close to data lines for compact design, then device complexity is reduced, but static electricity accumulation increases causing short circuits
Solution Approach 1:
The patent introduces intermediary protective structures between the data lines and load elements, such as shielding layers or discharge pathways. These intermediary elements act as mediators that prevent static electricity from accumulating on the load elements while maintaining the compact layout. The shielding layers provide electrostatic protection, and discharge pathways offer controlled routes for static electricity to safely dissipate, thereby preventing short circuits without increasing device complexity.
3Manufacturing precision
If multiple load elements are connected in series to extend data line coverage, then manufacturing precision is improved, but defect ratio increases due to charge accumulation
Solution Approach 1:
The patent segments the series-connected load elements into smaller groups or individual units, each with its own protection mechanism. Instead of having a single long series chain of load elements, the system divides them into modular segments that can be independently controlled and protected. This segmentation reduces the total charge accumulation risk in any single segment and allows for localized defect management, thereby maintaining manufacturing precision while reducing the overall defect ratio.
Solution Approach 2:
The patent implements protective measures in advance by incorporating discharge pathways and shielding structures during the design phase. These beforehand cushioning elements prevent charge accumulation before it can cause defects. The protective structures are built into the compact layout, providing preemptive protection against static electricity and charge-related failures, thus reducing the defect ratio while maintaining the benefits of extended data line coverage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design ensures consistent pixel luminance and prevents defects such as short circuits by controlling capacitance and charge accumulation, resulting in a high-quality display.
Implementation Method 1
a first capacitance between lower loads including the 1-1st lower load and the 1-2nd lower load and upper loads including the 1-1st upper load and the 1-2nd upper load may be different from a second capacitance between lower loads including the 2-1st lower load and the 2-2nd lower loads and upper loads including the 2-1st upper load and the 2-2nd upper load
Data Source
AI summary
A display apparatus includes: a substrate including a display area and a peripheral area outside the display area; a first data line extending from the display area into the peripheral area; a 1-1st lower load located in the peripheral area and electrically connected to the first data line; a 1-2nd lower load located in the peripheral area and electrically connected to the 1-1st lower load; a 1-1st upper load located in the peripheral area and above the 1-1st lower load, where the 1-1st upper load is insulated from the 1-1st lower load; and a 1-2nd upper load located in the peripheral area and above the 1-2nd lower load, where the 1-2nd upper load is insulated from the 1-2nd lower load and electrically connected to the 1-1st upper load.