Display Device Mask Reduction via Gate Electrode Merging
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Solution Overview
Problem
The manufacturing process of display devices, particularly OLEDs, requires a large number of masks, increasing processing costs and reducing efficiency.
Innovation Solution
A method and structure for reducing the number of masks used in the manufacturing process by forming a semiconductor pattern and conductive layers in a way that allows for concurrent processing of transistors and capacitors, using oxide semiconductors and specific layer configurations to minimize the need for additional mask steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional manufacturing processes are used for display devices, then transistors and capacitors can be formed with proper structure and function, but the number of masks required increases, leading to increased processing costs and reduced manufacturing efficiency
Solution Approach 1:
The patent combines the formation of transistors and capacitors into a unified manufacturing process. The gate electrode layer serves dual purposes: as the gate electrode for the transistor and as one electrode for the capacitor. This merging of functions reduces the number of separate mask patterns required, as the same conductive layer and mask steps are used to define both the transistor gate and capacitor electrode regions simultaneously.
Solution Approach 2:
The gate electrode layer is designed to serve multiple functions: it acts as the control gate for the transistor while simultaneously serving as one of the electrodes for the capacitor structure. This multi-functionality eliminates the need for separate electrode formation steps for the capacitor, reducing the overall mask count and simplifying the manufacturing process.
2Reliability
If additional mask steps are added to form separate capacitor electrodes, then capacitor structure can be properly formed, but processing costs increase and manufacturing efficiency decreases
Solution Approach 1:
The capacitor electrode is merged with the transistor gate electrode, forming a single integrated structure. The gate electrode layer is patterned using the same mask steps as the transistor gate, and this same layer serves as one electrode for the capacitor. This eliminates the need for additional mask steps specifically for capacitor electrode formation, maintaining productivity while ensuring proper capacitor structure.
Solution Approach 2:
The gate electrode layer is formed and patterned in advance to serve dual purposes. By establishing this conductive layer before separating the transistor and capacitor formation steps, the patent enables the same layer to function as both the transistor gate and capacitor electrode, avoiding later additional masking operations.
3Device complexity
If the gate electrode layer is used as one electrode for the capacitor, then the number of masks is reduced, but the transistor and capacitor structures must be carefully integrated
Solution Approach 1:
The patent applies different local configurations to the gate electrode layer depending on the region. In the transistor region, the gate electrode layer forms the control gate with proper spacing from the semiconductor channel. In the capacitor region, the same layer serves as one electrode with the semiconductor layer forming the other electrode. This local differentiation allows the same layer to serve multiple functions while maintaining proper structure in each region.
Solution Approach 2:
The gate electrode layer is segmented into different functional regions: one portion serves as the transistor gate electrode while another portion serves as the capacitor electrode. The semiconductor layer is also segmented to form the capacitor electrode in the capacitor region while forming the transistor channel in the transistor region. This segmentation allows proper structure integration with reduced mask complexity.
Data Source
AI summary
A display device includes a substrate, a first semiconductor pattern on the substrate and including a semiconductor layer of a first transistor, a first gate insulator on the substrate, a first conductive layer on the first gate insulator and including a first gate electrode of the first transistor and a first electrode of the capacitor connected to the first gate electrode of the first transistor, a first interlayer dielectric on the first gate insulator, a second semiconductor pattern on the first interlayer dielectric and including a semiconductor layer of a second transistor and a second electrode of the capacitor, a second gate insulator on the first interlayer dielectric, a second conductive layer on the second gate insulator and including a gate electrode of the second transistor and a third semiconductor pattern between the second semiconductor pattern and any one of the first conductive layer and the second conductive layer.