Display Device Mask Reduction via Merged Gate and Capacitor Electrodes
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Solution Overview
Problem
The manufacturing process of display devices requires a large number of masks, increasing costs and reducing process efficiency.
Innovation Solution
A display device design that reduces the number of masks used by forming multiple conductive and insulating layers simultaneously, such as the first and second conductive layers including gate electrodes and electrodes of a capacitor, and interlayer insulating films, allowing for concurrent formation of transistors and capacitors using fewer masks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple masks are used in the manufacturing process to form gate electrodes and capacitor electrodes separately, then the manufacturing precision and reliability are improved, but the manufacturing cost increases and process efficiency decreases
Solution Approach 1:
The patent combines the formation of gate electrodes and capacitor electrodes into a single conductive layer that is patterned using one mask. This merging of previously separate fabrication steps reduces the total number of masks required while maintaining the functional separation of gate and capacitor electrodes through selective patterning of the unified conductive layer.
Solution Approach 2:
The conductive layer serves multiple functions simultaneously - it forms both gate electrodes for transistors and electrode patterns for capacitors. This multi-functional approach allows a single mask to define multiple different structural elements that would traditionally require separate masks, thereby improving process efficiency without sacrificing manufacturing precision.
2Manufacturing precision
If multiple masks are used in the manufacturing process to form gate electrodes and capacitor electrodes separately, then the manufacturing precision is improved, but the manufacturing cost increases
Solution Approach 1:
The patent merges the formation of gate electrodes and capacitor electrodes into a single conductive layer that is patterned using one mask. This merging of previously separate fabrication steps reduces the total number of masks required while maintaining the functional separation of gate and capacitor electrodes through selective patterning of the unified conductive layer.
Solution Approach 2:
The patent discards the need for separate masks for gate and capacitor electrode formation by using a single mask that defines both structures. The unused portions of the conductive layer are removed through selective etching or lifting-off processes, recovering the ability to create distinct electrode patterns without requiring additional masking steps.
3Reliability
If multiple masks are used in the manufacturing process, then the reliability of the display device is improved, but the number of process steps increases and productivity decreases
Solution Approach 1:
The patent combines the formation of gate electrodes and capacitor electrodes into a single conductive layer that is patterned using one mask. This merging of previously separate fabrication steps reduces the total number of masks required while maintaining the functional separation of gate and capacitor electrodes through selective patterning of the unified conductive layer.
Solution Approach 2:
The conductive layer is deposited and preliminarily patterned to include both gate electrode regions and capacitor electrode regions in a single masking step. This preliminary action establishes both structures simultaneously, eliminating the need for subsequent separate patterning operations and reducing overall process time while maintaining reliability.
Data Source
AI summary
A display device includes a substrate, a first semiconductor layer on the substrate, a first gate insulating film on the first semiconductor layer, a first conductive layer on the first gate insulating film and including a first gate electrode and a first electrode of a capacitor connected to the first gate electrode, a second semiconductor layer on the first gate insulating film and at a different layer from the first semiconductor layer, a second gate insulating film on the first conductive layer and the second semiconductor layer, a second conductive layer on the second gate insulating film and including a second gate electrode and a second electrode of the capacitor, a second interlayer insulating film on the second conductive layer, and a third conductive layer on the second interlayer insulating film and including a first source electrode, a first drain electrode, a second source electrode, and a second drain electrode.