Display Memory Address Generation for Flexible Data Injection
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Solution Overview
Problem
Existing memory devices for display panels face operational mismatches due to differences in the number of data lines and source lines, leading to improper image data injection and timing issues.
Innovation Solution
A semiconductor memory device with a memory array, row and column selection units, and a selection address generating unit that allows for auto-mode operation based on internal signals, enabling flexible image data injection directions and sequences, even when the number of data lines differs from the number of source lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of data lines in the memory array is made equal to the number of source lines in the display panel, then timing matching between memory device and display panel is achieved, but the memory device loses flexibility in adapting to different display panel configurations and injection directions
Solution Approach 1:
The patent implements dynamic adaptability by providing multiple operational modes (normal mode and auto mode) that allow the memory device to dynamically adjust its address generation and data injection behavior based on the specific display panel configuration. In auto mode, the memory device can adapt to different numbers of source lines and injection directions without requiring physical reconfiguration, thus maintaining timing matching while preserving flexibility.
Solution Approach 2:
The patent changes operational parameters (address generation mode, injection direction, sequence) to resolve the contradiction. By switching between normal mode (external address control) and auto mode (internal address generation with configurable parameters), the memory device can maintain timing matching for the current configuration while being adaptable to future configuration changes through parameter reconfiguration rather than physical redesign.
2Adaptability or versatility
If the memory device supports multiple image data injection directions and sequences, then versatility with different display panels is improved, but complexity of address management and timing control increases
Solution Approach 1:
The patent applies self-service by implementing an auto mode where the memory device automatically generates row and column addresses internally without requiring external address inputs. The auto address generating unit self-manages the complex address management for multiple injection directions and sequences, reducing the burden on external controllers while maintaining versatility. The system serves itself by autonomously handling address generation, timing control, and injection sequence management.
Solution Approach 2:
The patent introduces an intermediary auto address generating unit that mediates between the external controller and the memory array. This intermediary handles the complex address management and timing control internally, translating high-level operational modes into detailed address sequences. The intermediary absorbs the complexity of multi-directional address management while presenting a simplified interface to external controllers.
3Ease of operation
If auto mode with internal signal generation is implemented, then ease of operation is improved, but device complexity increases due to additional address generation circuits
Solution Approach 1:
The patent implements universality by designing the auto address generating unit to handle multiple functions: generating row addresses, generating column addresses, controlling injection directions, and managing timing sequences. This multi-functional unit consolidates what would otherwise require separate circuits for each function, reducing overall device complexity while providing ease of operation through unified internal control.
Data Source
AI summary
A memory device includes a row selection unit for selecting word lines of a memory array, a column selection unit for selecting data lines of the memory array, a last address storing unit for storing a last row address and a last column address, and a selection address generating unit for providing a row selection address and a column selection address to select the word lines and the data lines. In the memory device, start row and column addresses are determined based on the first and last row addresses, the first and last column addresses, the row section address and the column selection address and forwardly or backwardly counted based on directions corresponding to image data injection directions in a display panel to which the memory device provides the image data.