Shared Display Memory Control for Smooth Controller Mode Switching
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Solution Overview
Problem
When multiple controllers share a memory, there is a failure in smooth mode switching, leading to temporary shutoff of the display screen or the need for resetting the display power.
Innovation Solution
A display device and controller system that enables smooth mode switching by detecting a first mode period using chip selection and memory enable signals, and controlling a second controller to a high-impedance state during this period, utilizing edge detection circuits and logic gates to manage memory access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple controllers share one memory, then resource utilization is improved, but mode switching reliability deteriorates causing display shutoff or power reset
Solution Approach 1:
A mode control signal generation circuit is introduced as an intermediary between the first controller and the second controller. This circuit receives mode enable signals and chip selection signals from the first controller, generates appropriate mode control signals, and controls the second controller's access to the shared memory. The intermediary ensures reliable mode switching by coordinating memory access between multiple controllers without causing display shutoff or power reset.
Solution Approach 2:
The mode control signal generation circuit performs preliminary actions by detecting mode enable edges and chip selection edges in advance before memory access operations. By detecting these signal edges and generating mode control signals beforehand, the system prepares the memory access state in advance, preventing conflicts during mode switching and ensuring smooth transitions between controllers.
2Adaptability or versatility
If mode switching is implemented between multiple controllers, then functional versatility is improved, but power consumption increases due to unnecessary driving loss
Solution Approach 1:
The system implements periodic action by controlling the second controller to operate only during specific periods when the first controller is not using the memory. The mode control signal generation circuit generates enable signals based on detected signal edges, activating the second controller only when needed and placing it in high-impedance state during the first controller's memory access period, thereby reducing unnecessary power consumption.
Solution Approach 2:
The patent applies local quality by placing the second controller in a high-impedance state (disconnected state) during the first controller's memory access period, while keeping it operational during periods when the first controller is not using the memory. This selective activation based on local timing conditions reduces power consumption by eliminating unnecessary driving loss during periods when the second controller is not needed.
3Adaptability or versatility
If a second controller shares memory with a first controller, then system integration is improved, but control authority determination becomes complex
Solution Approach 1:
The mode control signal generation circuit implements self-service by autonomously determining control authority based on signal edge detection. The circuit automatically detects mode enable edges and chip selection edges, generates appropriate mode control signals, and manages the second controller's memory access without requiring complex external arbitration or manual intervention, simplifying control authority determination.
Solution Approach 2:
The system uses feedback mechanisms where the mode control signal generation circuit continuously monitors mode enable signals and chip selection signals from the first controller, detects their edges, and adjusts the second controller's memory access permissions accordingly. This feedback-based control automatically manages control authority determination based on the first controller's actual memory usage state.
Data Source
AI summary
A display device can include a display panel having a plurality of subpixels, a memory storing image control data for controlling an image displayed on the display panel, a mode control signal generation circuit generating a mode control signal based on a first mode signal supplied from a first controller, and a second controller configured to share the memory with the first controller and determine a control authority of the first controller for the memory through the mode control signal.