Display Memory Write Path Segmentation for Manufacturing Efficiency
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Solution Overview
Problem
The existing manufacturing process for display devices is inefficient due to the time-consuming process of writing correction data to the memory, which delays the manufacturing process and requires powering on the device.
Innovation Solution
A display device design that includes a terminal unit to transmit correction data and memory voltage from an external device during a first period, with a timing controller disabled during writing, and a switch unit to electrically connect the terminal unit and memory, allowing for writing correction data without powering on the device, thereby reducing the time required for stabilization and manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the timing controller is enabled during the writing of correction data to the memory, then the device can be powered on and operate normally, but the manufacturing process time is extended and efficiency is reduced
Solution Approach 1:
The patent segments the control system into two independent paths: a write signal line that directly connects the terminal unit to the memory for correction data writing, and a separate interface line for normal display operations. The timing controller is excluded from the write path, allowing independent operation. This segmentation enables correction data writing without powering on the timing controller, improving manufacturing efficiency while maintaining device reliability.
Solution Approach 2:
The patent introduces a write signal line as an intermediary communication path between the terminal unit and the memory. This dedicated write path bypasses the timing controller, allowing correction data to be written directly to the memory during manufacturing without requiring the timing controller to be powered on or stabilized, thus resolving the contradiction between reliability and productivity.
2Reliability
If the timing controller is stabilized before writing correction data, then writing operations can proceed reliably, but the stabilization time increases the overall writing time
Solution Approach 1:
The patent implements preliminary action by providing a memory voltage line that supplies voltage to the memory independently before and during the correction data writing process. This preliminary voltage provision ensures the memory is ready to receive data immediately when the write signal is activated, eliminating the need to wait for the timing controller to stabilize, thus reducing writing time while maintaining reliability.
Solution Approach 2:
The patent segments the power supply system into a dedicated memory voltage line that operates independently from the timing controller power supply. This segmentation allows the memory to be powered and stabilized separately and earlier than the timing controller, enabling immediate data writing upon write signal reception without waiting for timing controller stabilization.
3Productivity
If a dedicated write signal line is implemented to bypass the timing controller, then writing speed improves, but the device complexity increases
Solution Approach 1:
The terminal unit is designed with multi-functionality, serving both as a data source for correction data writing and as a control interface for normal display operations. The write signal line, while dedicated for writing, uses the existing terminal unit infrastructure, thereby achieving improved writing speed without proportionally increasing overall device complexity.
Solution Approach 2:
The write signal line acts as a simple intermediary connection that directly links the terminal unit to the memory. This intermediary path is straightforward in design, requiring minimal additional components, thus achieving fast writing speed while keeping the increase in device complexity minimal.
Data Source
AI summary
A display device may include a memory configured to store correction data during a first period, a timing controller configured to generate second data by correcting the first data using the correction data, during a second period, and a terminal unit configured to transmit, to the memory, the correction data and a memory voltage received from an external device, during the first period. During the first period, the memory may be supplied with the memory voltage through a memory voltage line and driven by the memory voltage.