Display Module Notch Conductor Routing for Narrow Bezel
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing display technologies face challenges in achieving a narrow bezel due to the need for a Chip on Film (COF) to be designed on one side of the display panel, leading to a large non-display area and increased black bezel width, which reduces the screen-to-body ratio and increases the risk of screen cracking during drops.
Innovation Solution
The implementation of a display module with notches on the array substrate's outer edge for conductor routing, allowing the drive circuit to connect to the main control board without increasing the bezel width, and a similar approach on the opposite substrate for touch circuits, reducing the need for full through holes and minimizing bezel formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If COF is designed on one side of the display panel to output the drive circuit, then the drive circuit can be connected to the mainboard, but a non-display area at the edge is increased, causing a large black bezel
Solution Approach 1:
The patent transitions from a planar COF layout to a three-dimensional conductor structure by etching notches into the array substrate. The conductor extends vertically through the substrate thickness, allowing electrical connection without occupying lateral display area, thus resolving the contradiction between manufacturability and display area.
Solution Approach 2:
The conductor is nested within the array substrate by etching notches that penetrate through the substrate. This nesting approach allows the conductor to be embedded in the substrate structure itself, eliminating the need for external COF components and reducing the non-display area while maintaining connection functionality.
2Reliability
If full through holes are used for conductor routing, then electrical connection is achieved, but the risk of screen cracking in dropping process increases
Solution Approach 1:
The patent applies local quality by creating notches with controlled depth and geometry rather than uniform full through holes. The notch dimensions and shape are optimized locally to provide sufficient electrical connection while minimizing stress concentration points that would lead to cracking during drops.
3Reliability
If FOG connection process is used to connect drive circuit to mainboard, then electrical connection is achieved, but quantities of FPCs and glass substrates increase, and process complexity increases
Solution Approach 1:
The patent merges the conductor function with the array substrate structure by etching notches directly into the substrate. This integration eliminates the need for separate FOG, FPC, and additional glass substrate components, reducing overall device complexity while maintaining reliable electrical connection between the drive circuit and mainboard.
Data Source
AI summary
A display includes at least an array substrate, and the array substrate has a drive circuit layer. At least one first notch is provided on an outer edge of a lead-out side of the array substrate, and a first conductor is disposed in each first notch. A first end of the first conductor is in contact with a lead end of the drive circuit layer, and a second end of the first conductor extends along the first notch to a back side of the array substrate.