Display Module Test Signal Routing for COP Connection Resistance

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Solution Overview

Problem

In display modules, particularly those with integrated circuits mounted directly on the display panel in a Chip-On-Plastic (COP) structure, connection resistances between the display panel and the integrated circuit, as well as between the display panel and the printed circuit board, pose challenges for efficient performance and testing.

Innovation Solution

The display module incorporates a printed circuit board with an improved design that enables the performance of a connection resistance test. This design includes output terminals electrically connected to output pad groups on the display panel, allowing for the measurement of resistance between the driving circuit chip and the display panel, as well as between the printed circuit board and the display panel.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If the integrated circuit is mounted directly on the display panel in a COP structure, then the display area ratio is increased, but connection resistance is generated between the display panel and the integrated circuit

Engineering Contradiction:
Improvedisplay area ratioVSAvoidconnection resistance
Core Design Contradiction:
Area of moving objectVSReliability

Solution Approach 1:

A test signal line is introduced as an intermediary element between the display panel and the integrated circuit. This test signal line serves as a mediator to measure and evaluate the connection resistance that inherently exists in the COP structure, allowing the system to maintain direct mounting while enabling resistance testing through the added test pathway.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Area of moving object

If the printed circuit board is disposed on the display panel in a FOP or FOG structure, then the display area ratio is increased, but connection resistance is generated between the display panel and the printed circuit board

Engineering Contradiction:
Improvedisplay area ratioVSAvoidconnection resistance
Core Design Contradiction:
Area of moving objectVSReliability

Solution Approach 1:

The test signal line acts as an intermediary pathway between the display panel and the printed circuit board. By routing test signals through this dedicated line, the system can measure the connection resistance introduced by the FOP/FOG structure without compromising the area efficiency benefits of these mounting approaches.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Device complexity

If the integrated circuit is mounted directly on the display panel, then device complexity is reduced, but the ability to measure connection resistance is lost

Engineering Contradiction:
Improvestructure complexityVSAvoidconnection resistance measurement
Core Design Contradiction:
Device complexityVSDifficulty of detecting and measuring

Solution Approach 1:

Test signal lines are incorporated into the design during the preliminary design phase, before the actual mounting of the integrated circuit. This preliminary action ensures that the measurement capability is built into the structure from the beginning, allowing simple direct mounting to proceed while maintaining the ability to measure connection resistance through the pre-configured test pathways.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20250133948A1Display module
Publication Date: 2025.04.24 SAMSUNG DISPLAY CO LTD
  • US20250133948A1 patent drawing
  • US20250133948A1 patent drawing
  • US20250133948A1 patent drawing

AI summary

A display module includes: a display panel including a plurality of output pad groups each output pad group of the plurality of output pad groups including a first output pad; and a driving circuit chip disposed on the display panel and overlapping the output pad groups; a printed circuit board disposed on the display panel, the printed circuit board including a plurality of output terminals electrically connected to the plurality of output pad groups. The plurality of output terminals include a first output terminal electrically connected to the first output pad of each of the plurality of output pad groups.