Display Multiplexer Control Line Time Constant Reduction
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Solution Overview
Problem
High-definition display devices face signal delay issues due to longer signal paths from the driver IC to multiplexer switches, leading to increased time constants and reduced display quality and efficiency.
Innovation Solution
The implementation of a display apparatus with a multiplexer circuit, driving unit, and control lines where the maximum time constant from the driving unit to the switch units is less than R*C/4, achieved by strategically placing first and second control lines to minimize equivalent resistance and capacitance, thereby reducing signal delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the definition is increased to FHD (1080*1920), then the display quality is improved, but the charging time of each data line becomes shorter and the signal delay problem worsens
Solution Approach 1:
The patent divides the control line into multiple segments by introducing a buffer unit between the driving unit and the multiplexer circuit. This segmentation allows the control signal to be transmitted in stages, reducing the overall time constant and signal delay while maintaining FHD display quality.
Solution Approach 2:
The buffer unit acts as an intermediary component between the driving unit and the multiplexer circuit. It receives the control signal from the driving unit and retransmits it to the multiplexer circuit, thereby reducing the time constant and signal delay without compromising the high-definition display quality.
2Productivity
If the scan frequency is increased to 60 times per second, then the display refresh rate is improved, but the charging time of each data line becomes shorter and signal delay increases
Solution Approach 1:
The control line is segmented by introducing a buffer unit that divides the signal transmission path. This allows the control signal to reach the multiplexer circuit faster by reducing the effective time constant, enabling higher scan frequencies of 60 times per second while maintaining adequate charging time for data lines.
Solution Approach 2:
The buffer unit serves as an intermediary that optimizes the control signal transmission. It receives the control signal from the driving unit and retransmits it to the multiplexer circuit with reduced delay, facilitating high scan frequencies of 60Hz while ensuring sufficient charging time for data lines.
3Device complexity
If the multiplexer bus is disposed on the display panel, then the device integration is improved, but the maximum time constant occurs at the central portion and signal delay increases
Solution Approach 1:
The buffer unit is introduced as an intermediary component between the driving unit and the multiplexer circuit. It receives the control signal from the driving unit and retransmits it to the multiplexer circuit, thereby reducing the maximum time constant that occurs at the central portion of the multiplexer bus and minimizing signal delay while maintaining panel integration.
Data Source
AI summary
A display apparatus includes a multiplexer circuit, a driving unit, a first control line and a second control line. The multiplexer circuit includes a plurality of switch units. The first control line is electrically connected with the switch units and the driving unit. The second control line is electrically connected with the switch units and the driving unit. A maximum time constant from the driving unit to the switch units is less than R*C/4, wherein R represents the equivalent resistance of the portion of the first control line between the two switch units which are the farthest from each other, and C represents the equivalent capacitance of the portion of the first control line between the two switch units which are the farthest from each other.