Display Panel Multiplexer Timing for Touch Noise Reduction

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Solution Overview

Problem

Display panels experience noise interference due to drive signals, which affects their performance, especially when operating with touch functions, as noise is generated during data line charging and discharging, gate drive signals, and source control signals, leading to disruptions in signal transmission.

Innovation Solution

The display panel incorporates a multiplexer circuit with two switch sets, each controlled by distinct clock signals with overlapping and asynchronous enabling periods, dispersing energy to reduce noise. The clock signals for the first and second switch sets have delayed rising edges, ensuring that energy is dispersed when switches are turned on, thereby minimizing noise generation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If data lines are charged or discharged with drive signals, then the display panel operates normally, but noise is generated that interferes with touch signals

Engineering Contradiction:
Improvedisplay panel operationVSAvoidnoise interference
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The multiplexer circuit divides the data line driving into multiple switch sets (first switch set and second switch set), each controlled by different clock signals. This segmentation allows alternating operation of switch sets, distributing the charging/discharging events over time and reducing peak noise levels that would occur if all data lines were driven simultaneously.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The circuit employs periodic alternating operation of the first and second switch sets using clock signals with different phases. The first switch set operates during one time period while the second switch set operates during another time period, creating a periodic pattern that distributes noise generation over time and reduces continuous noise interference.

Inventive Principle:
Principle #19Periodic action

2Productivity

If multiple switches are turned on simultaneously, then data transmission efficiency is high, but noise generation increases

Engineering Contradiction:
Improvedata transmission efficiencyVSAvoidnoise generation
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The first and second clock signals control their respective switch sets in alternating periodic fashion. During each clock cycle, one switch set is turned on while the other is off, and they switch roles in the next cycle. This periodic alternation maintains data transmission efficiency by keeping switches operational while distributing noise generation across different time periods.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The circuit design anticipates noise generation by alternating the operation timing of different switch sets. Before any single switch set operates, the other switch set is already prepared and will take over subsequently, ensuring continuous data transmission while pre-distributing the noise events in time.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10679541B2Display panel
Publication Date: 2020.06.09 AU OPTRONICS CORP
  • US10679541B2 patent drawing
  • US10679541B2 patent drawing
  • US10679541B2 patent drawing

AI summary

A display panel includes a plurality of data lines and a multiplexer circuit including a first switch set and a second switch set each having a plurality of switches. Each switch of the switch sets has a first end connected to the data lines and a second end. The second ends of a same switch set are connected to each other to form a receiving end connected to a data signal source. The first switch set is turned on alternately by a first clock signal and a second clock signal. The second switch set is turned alternately by a third clock signal and a fourth clock signal. The enabling period of the first clock signal and that of the third clock signal partially overlap and have asynchronous starting times. The enabling period of the second clock signal and that of the fourth clock signal at least partially overlap.