Display MUX Control-Line Layout to Reduce Parasitic Capacitance

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The use of multiplexers in display devices leads to electro-magnetic interference (EMI) and parasitic capacitance due to overlapping control signal lines, causing RC delay and charging system defects.

Innovation Solution

A display device design that includes a multiplexer and a pseudo multiplexer with non-overlapping control lines, using control signals with opposite waveforms to minimize parasitic capacitance and RC delay.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If control signal lines of the multiplexer and pseudo multiplexer are arranged to overlap, then wiring space is reduced, but parasitic capacitance increases causing RC delay

Engineering Contradiction:
Improvewiring spaceVSAvoidsignal transmission accuracy
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The patent transitions from two-dimensional planar arrangement to three-dimensional stacked arrangement by placing MUX control lines and pseudo MUX control lines on different layers (first and second signal lines respectively), allowing overlapping in plan view while maintaining electrical isolation through vertical separation

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent implements nested structure where control lines are arranged in hierarchical layers - the first signal line layer contains MUX control lines, while the second signal line layer contains pseudo MUX control lines, with insulating films nesting between these layers to provide isolation while maintaining compact overall structure

Inventive Principle:
Principle #7Nested doll (Nesting)

2Reliability

If control signal lines are separated into different regions, then parasitic capacitance is reduced, but wiring complexity increases

Engineering Contradiction:
Improvesignal transmission accuracyVSAvoidwiring structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the routing of MUX control lines and pseudo MUX control lines into a unified multi-layer signal line structure, where both types of control lines share the same wiring region but are separated vertically by insulating films, reducing overall wiring complexity compared to completely separate routing

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent segments the control signal transmission paths by assigning MUX control lines to the first signal line and pseudo MUX control lines to the second signal line, with insulating films creating distinct transmission channels that can be independently optimized

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Prevents or reduces RC delay and improves the normal transmission of control signals, enhancing the charging system performance.

Implementation Method 1

as a line that transmits a control signal of the pseudo-multiplexer overlaps a line that transmits a control signal of the multiplexer, parasitic capacitance occurs, which causes RC delay

Methodology Applied
Scientific EffectParasitic capacitance: Capacitance

Data Source

PatentUS12424186B2Display device
Publication Date: 2025.09.23 LG DISPLAY CO LTD
  • US12424186B2 patent drawing
  • US12424186B2 patent drawing
  • US12424186B2 patent drawing

AI summary

A display device includes: a multiplexer in a first region of a non-display region, and including K MUX transistors which are commonly connected to a data channel line and are connected to K data lines; a pseudo multiplexer disposed in a third region of the non-display region, and including K pseudo MUX transistors corresponding to the K MUX transistors; and K MUX control lines and K pseudo MUX control lines in a second region between the first and third regions, the K MUX control lines connected to the K MUX transistors, the K pseudo MUX control lines connected to the K pseudo MUX transistors, wherein the second region includes a first partial region adjacent to the first region and having the K MUX control lines thereon, and a second partial area adjacent to the third region and having the K pseudo MUX control lines thereon.