Display Device On-Bias Voltage Control for Luminance Uniformity
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Solution Overview
Problem
Display devices experience quality degradation due to leakage current and hysteresis characteristics of driving transistors, leading to luminance differences across the display panel, especially when on-bias voltage is supplied multiple times during active and blank periods.
Innovation Solution
A display device configuration that includes a power supply to provide different voltage levels for on-bias power and initialization power during active and blank periods, with a dimming period for gradual voltage changes, controlled by a timing controller to manage scan and data drivers, ensuring consistent luminance across the panel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If on-bias voltage is supplied multiple times during active and blank periods to compensate for leakage current and hysteresis, then display uniformity is improved, but luminance difference appears at the boundary between active and blank periods
Solution Approach 1:
The patent applies parameter changes by adjusting the voltage level of on-bias power from a first voltage level during the active period to a second voltage level during the blank period. This gradual voltage transition through a dimming period prevents abrupt changes that cause luminance differences at boundaries, while still maintaining multiple on-bias applications to compensate for leakage current and hysteresis effects.
Solution Approach 2:
The patent implements dynamics by introducing a dimming period where the on-bias power voltage level dynamically transitions from the first voltage level to the second voltage level. This dynamic adjustment allows the system to adapt to different operational phases (active vs. blank periods) and prevents luminance boundary issues while maintaining display uniformity through controlled voltage changes.
2Illumination intensity
If on-bias voltage timing is adjusted to prevent overlap between active and blank periods, then luminance boundary issues are reduced, but display uniformity compensation becomes less effective
Solution Approach 1:
The patent resolves this contradiction by changing the voltage parameter rather than simply adjusting timing. The on-bias power voltage level is changed from a first level to a second level during the blank period, with a dimming transition period. This allows continuous or overlapping timing to maintain compensation effectiveness while the voltage level change prevents luminance boundary differences.
3Illumination intensity
If different voltage levels are used for on-bias power during active and blank periods, then luminance fluctuations are minimized, but power consumption increases
Solution Approach 1:
The patent applies parameter changes by using different voltage levels for on-bias power during active and blank periods. A first voltage level is used during the active period and a second voltage level during the blank period, with a dimming period for gradual transition. This minimizes luminance fluctuations while the voltage reduction during blank periods helps manage power consumption compared to maintaining high voltage continuously.
Data Source
AI summary
A display device includes a display panel including pixels coupled to a first scan line and a data line, a power supply to supply voltages, a scan driver to provide a first scan signal to the first scan line a plurality of times for a first frame period (FFP), a data driver to supply a data signal to the data line, and a timing controller to control driving of components. The FFP includes: a first active period (FAP), in which the data signal is supplied; and a first blank period (FBP), in which the data signal is not supplied. The power supply provides on-bias power having a first voltage level (FVL) in the FAP, and provides on-bias power having a second voltage level (SVL) in the FBP. The FBP following the FAP includes a first dimming period in which the on-bias power gradually changes from the FVL to the SVL.