Display Device Overlapping Via Holes Reduce Dead Space

The patent transitions from a planar two-dimensional layout to a three-dimensional stacked architecture. Connection patterns are arranged across multiple layers (first, second, third connection patterns) connected by via holes, allowing data lines to route vertically through the substrate thickness rather than only horizontally across the surface. This dimensional change enables compact pixel circuit integration that reduces dead space while maintaining driver placement flexibility.

The patent implements nested structures where via holes are positioned within or adjacent to connection patterns, and connection patterns are layered within insulating layers. Specifically, via holes penetrate through insulating layers to connect different conductive layers, creating a nested arrangement that maximizes space utilization. This nesting allows the driver area to be more efficiently packed without increasing the overall footprint or dead space.

The data line routing is segmented into multiple independent conductive layers (first data conductive layer, second data conductive layer, third data conductive layer), each handling specific routing functions. This segmentation allows complex routing paths to be divided into manageable segments across different layers, with via holes providing vertical connections between segments. The complexity is distributed across layers rather than concentrated in a single plane, making the overall routing more manageable despite the reduced dead space.

Insulating layers serve as intermediaries between conductive layers, providing both electrical isolation and structural support for via holes. The insulating layers enable the data lines to pass through the substrate in an organized manner by mediating between different conductive layers. This intermediary structure simplifies the routing complexity by providing predefined pathways and isolation, rather than requiring direct routing between all components.