Display Module Package Layout for Thin, Low-Latency Panels
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Solution Overview
Problem
Current display modules for small-sized electronic devices face challenges in reducing thickness, size, and response delay time while maintaining high resolution and functionality.
Innovation Solution
A display module package is designed with a first and second wiring layer structure, a semiconductor chip, molding members, and a light emitting device array, where the second wiring layer is connected to the first through a vertical connection electrode, and the light emitting device array is sealed by a second molding member to expose the light emitting devices, reducing thickness and signal transfer distance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If a conventional display module structure is used, then the display functionality is maintained, but the thickness and size cannot be reduced
Solution Approach 1:
The patent combines multiple functional layers (wiring layers, semiconductor chip, light emitting devices, molding members) into a single integrated display module package structure. This merging approach reduces the overall thickness and size while maintaining all necessary display functions, directly resolving the contradiction between reducing dimensions and maintaining functionality.
Solution Approach 2:
The patent employs a nested structure where the semiconductor chip is disposed on the first wiring layer structure, the light emitting device array is disposed on the second wiring layer structure, and molding members encapsulate these components. This nesting arrangement optimizes space utilization and reduces overall package thickness while preserving functional integrity.
2Loss of time
If the wiring layer distance is reduced, then the response delay time is reduced, but the manufacturing precision requirements increase
Solution Approach 1:
The patent introduces vertical connection electrodes as intermediary elements that electrically connect the first wiring layer structure to the second wiring layer structure. These electrodes are disposed between the wiring layers and enable short signal transmission paths, reducing response delay time while the molding members provide structural support that facilitates precise alignment during manufacturing.
Solution Approach 2:
The patent changes the spatial arrangement parameter by reducing the vertical distance between the first and second wiring layer structures. This parameter change directly reduces the signal transmission path length, thereby reducing response delay time. The molding members are designed to maintain this reduced spacing while ensuring manufacturing feasibility through proper encapsulation and support.
3Use of energy by moving object
If the light emitting devices are exposed, then the light emission efficiency is improved, but the protection of internal components is reduced
Solution Approach 1:
The patent uses molding members to segment the package structure, creating distinct functional zones: an exposed region where light emitting devices are accessible for light emission, and encapsulated regions where internal components (wiring layers, semiconductor chip, vertical connection electrodes) are protected. This segmentation allows simultaneous achievement of high light emission efficiency and component reliability.
Solution Approach 2:
The molding members provide localized protection only where needed - encapsulating the internal wiring structures and semiconductor chip while leaving the light emitting device regions exposed. This local quality approach ensures that protection is applied selectively, maintaining light emission efficiency in exposed areas while providing reliability protection in enclosed areas.
Data Source
AI summary
A display module package includes a semiconductor chip, a wiring member disposed on the semiconductor chip, including an insulating layer and a wiring layer, and contacting at least a portion of the semiconductor chip, a light emitting device array disposed on the wiring member and including a plurality of light emitting devices disposed on one surface, wherein the wiring member is between the semiconductor chip and the light emitting device, and a molding member disposed on the wiring member, sealing part of the light emitting device array, and having an opening for exposing the plurality of light emitting devices.