Display Driver Pad Layout for Narrow-Bezel Fan-Out Routing
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Solution Overview
Problem
The challenge of maintaining a substantially narrow bezel in display screens is hindered by the need for numerous hard-wired connections between display and capacitive sense elements and the electrical circuit, which increases the fan-out area height, contradicting the trend towards bezel-less or nearly bezel-less designs.
Innovation Solution
The implementation of a new output pad sequence design on a driver chip, coupled via chip-on-glass bonding, adjusts interconnect routing to access pads from side edges instead of the top edge, reducing the fan-out area height and bezel width by using multiple driver chips and optimizing interconnect layouts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If numerous hard-wired connections are used between display elements and electrical circuit, then electrical connectivity is ensured, but fan-out area height increases
Solution Approach 1:
The patent transitions from a single-row pad arrangement (one-dimensional routing) to a multi-row pad arrangement (two-dimensional routing). Multiple rows of pads are distributed across the driver chip, allowing interconnects to access pads from different locations rather than all from one edge. This dimensional change enables more efficient routing paths and reduces the height required for the fan-out area while maintaining all necessary electrical connections.
Solution Approach 2:
The patent segments the pad arrangement into multiple rows and groups, with different subsets of pads located at different positions on the driver chip. This segmentation allows interconnects to be divided into different groups that access different pad rows, enabling parallel routing paths and reducing the concentration of routing demands at a single location, thereby reducing fan-out area height.
2Device complexity
If all interconnects access pads from a single edge, then routing is simplified, but fan-out area height increases
Solution Approach 1:
The patent moves from one-dimensional edge-based access to two-dimensional multi-edge access. Pads are arranged in multiple rows that can be accessed from different edges of the driver chip. This allows interconnects to approach pads from multiple directions (top, bottom, left, right edges), creating a more distributed routing topology that reduces the vertical height requirement while managing routing complexity through spatial distribution.
Solution Approach 2:
The patent introduces flexibility in interconnect routing by allowing different interconnects to access pads from different edges based on their destination. This dynamic routing approach adapts the access path to the specific connection requirements, optimizing the fan-out area utilization and reducing overall height while maintaining manageable routing complexity through rule-based assignment.
Data Source
AI summary
An electronic device has a display substrate including a display area, a driver area, and a fan-out area. The fan-out area has interconnects that provide electrical accesses to display elements on the display area. A driver chip is disposed on the driver area and includes a first edge adjacent to the display area, two side edges connected to the first edge, and a plurality of pad groups. Each pad group includes a row of electronic pads that are electrically coupled to a subset of display elements via a subset of interconnects routed on the fan-out area. The pad groups include a first pad group and a second pad group disposed immediately adjacent to the first pad group. A first subset of interconnects cross one of the two side edges, and extend above a gap between rows of the first and second pad groups to reach the first pad group.