Display Panel Pad Insulation Spacing for Peripheral Crack Resistance
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Solution Overview
Problem
As display panels become thinner and occupy more area, elements in the narrow peripheral area are prone to cracking, leading to reduced reliability and display quality degradation.
Innovation Solution
A display device design featuring a first organic insulating layer with an opening overlapping pad electrodes, a second organic insulating layer extending to overlap part of the integrated circuit, and a distance of at least 40 μm between the insulating layer edge and the integrated circuit edge, along with a stepped portion in the second layer to distribute stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If display panel area is increased and thickness is decreased, then application range is improved, but elements in peripheral area become prone to cracking
Solution Approach 1:
The patent applies different structural configurations to different regions of the display panel. Specifically, the gate electrode and signal line are positioned on opposite sides of the peripheral area, creating localized structural differences that prevent crack propagation while maintaining overall panel integrity. This regional differentiation allows the peripheral area to withstand stress without compromising the entire display panel.
2Area of stationary object
If elements are arranged in narrow peripheral area, then display area is increased, but reliability is reduced due to cracks
Solution Approach 1:
The patent segments the peripheral area structure by positioning the gate electrode and signal line on opposite sides, creating distinct functional zones. This segmentation prevents stress concentration at single locations and distributes mechanical loads across different regions, thereby reducing crack susceptibility while maximizing the display area.
3Reliability
If distance between insulating layer edge and integrated circuit edge is increased, then crack prevention is improved, but peripheral area space is reduced
Solution Approach 1:
The patent utilizes vertical layering to resolve the spatial conflict. By positioning the gate electrode and signal line on opposite sides in the planar dimension while maintaining appropriate distances, the design prevents crack propagation without excessively reducing peripheral space. This dimensional arrangement allows adequate spacing for reliability while preserving usable peripheral area.
Data Source
AI summary
A display device includes: a display area having a plurality of sub-pixels; a plurality of pad electrodes in a peripheral area outside the display area; a first organic insulating layer comprising an opening overlapping the plurality of pad electrodes; and an integrated circuit overlapping the plurality of pad electrodes and electrically connected to the plurality of pad electrodes, wherein a distance between an edge of the first organic insulating layer defining the opening and an edge of the integrated circuit is 40 micrometers (μm) or more.