Display Pad Layout With Shared Test Bumps to Reduce Dead Space
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Solution Overview
Problem
Conventional display devices require a large planar area for testing contact status between the substrate and driving integrated circuit, leading to increased dead space and inefficiency in inspection processes.
Innovation Solution
The display device incorporates a circuit wire that electrically connects first to sixth test bumps, reducing the number of test pads from sixteen to ten, allowing for effective inspection of contact status between the substrate and driving integrated circuit while minimizing dead space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional test pad configuration is used to inspect contact status, then contact inspection can be performed, but the planar area occupied by testing elements increases
Solution Approach 1:
The patent merges multiple test pad functions into a reduced set of test pads by introducing circuit wires that electrically connect multiple test bumps to fewer test pads. Specifically, the circuit wires connect test bumps that would otherwise require separate test pads, enabling contact status inspection with only 10 test pads instead of 16, thus reducing the planar area while maintaining inspection capability.
Solution Approach 2:
The patent introduces circuit wires as intermediary elements between test bumps and test pads. These circuit wires serve as mediators that allow electrical connection from multiple test bumps to a reduced number of test pads, enabling the contact status inspection function to be achieved with fewer test pads and less planar area.
2Reliability
If more test pads are used for comprehensive contact inspection, then inspection coverage is improved, but dead space increases
Solution Approach 1:
The patent combines multiple test bump connections into a reduced test pad array by using circuit wires as connection pathways. This merging approach maintains comprehensive inspection coverage across all test bumps while reducing the number of test pads from 16 to 10, thereby reducing dead space in the pad region.
Solution Approach 2:
The patent utilizes the circuit wire connections to create an additional dimensional layer of electrical connectivity. Instead of requiring direct one-to-one mapping between test bumps and test pads, the circuit wires provide indirect connections that span across the integrated circuit, enabling comprehensive coverage with fewer test pads and reduced dead space.
3Area of stationary object
If test pads are arranged sparsely to reduce dead space, then area efficiency improves, but connection complexity increases
Solution Approach 1:
The patent uses circuit wires as intermediary elements that simplify the connection structure. Rather than requiring complex direct connections from each test bump to its own test pad, the circuit wires provide organized pathways that connect multiple test bumps to shared test pads, reducing the overall number of connections and simplifying the connection structure while enabling sparse test pad arrangement.
Data Source
AI summary
A display device includes a substrate including a display region and a pad region, a driving integrated circuit contacting the substrate at the pad region and including first to third test bumps receiving test signals and a circuit wire connected to each of the first to third test bumps, test pads in the pad region, through which the test signals are provided to the driving integrated circuit and including first to tenth test pads, and connection wires in the pad region, through which the test signals are provided to the test bumps from the test pads and including a first connection wire connecting the first test pad to the first test bump, second and third connection wires connecting the second and third test pads, respectively, to the second test bump, and fourth and fifth connection wires connecting the fourth and fifth test pads, respectively, to the third test bump.