Display Panel Active Layer Conductorization via Via Holes
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Solution Overview
Problem
Conventional display panels face issues during wet etching processes where the metal etching solution damages the active layer, leading to contact resistance and failure in conduction due to the use of low-impedance metals, which cannot undergo dry etching.
Innovation Solution
A display panel design with a substrate layer, light shielding metal layer, buffer layer, active layer, and via holes defined by the gate insulating layer, where the source and drain widths are smaller than the active layer, allowing for increased conductorized area and enhanced edge contact through lateral diffusion during conductorization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If wet etching is used to prepare source, gate and drain in the same layer, then process complexity is reduced and costs are saved, but the metal etching solution damages the active layer causing contact resistance and conduction failure
Solution Approach 1:
The patent applies preliminary action by forming via holes in the gate insulating layer before depositing the source, gate and drain electrodes. This allows the active layer to be conductorized in advance through the via holes, creating conductive paths that protect against subsequent wet etching damage. The preliminary conductorization ensures reliable conduction even when wet etching is used to simplify the overall process.
Solution Approach 2:
The via holes filled with conductor material serve as intermediaries between the source/drain electrodes and the active layer. These intermediary conductive paths allow current to flow through the via holes, bypassing the damaged regions of the active layer that result from wet etching, thus maintaining conduction reliability while enabling process simplification.
2Manufacturing precision
If dry etching is used for gate insulating layer, then etching precision is improved, but the active layer is damaged twice causing source, drain and active layer to fail conduction
Solution Approach 1:
The patent performs preliminary conductorization of the active layer through via holes before the dry etching process. This ensures that conductive paths are established in advance, so even if the dry etching process damages the active layer, the pre-formed conductive paths through the via holes maintain electrical connection between source, gate and drain.
3Reliability
If source and drain widths are reduced below active layer width, then conductorized area is increased and edge contact is enhanced, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies local quality by making the source and drain electrode widths narrower than the active layer width, concentrating the contact area at specific edges of the active layer. This localized contact approach increases the conductorized area through lateral diffusion at the edges while maintaining precise dimensional control through the via hole positioning and selective width reduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design significantly improves conduction characteristics of the thin film transistor by increasing contact paths between the source, drain, and active layer, enabling effective mass production while avoiding damage from wet etching.
Implementation Method 1
By using a lateral diffusion phenomenon when the active layer is conductorized, the edge contact quality of the source, the drain, and the active layer is enhanced
Data Source
AI summary
A display panel, a method for preparing a display panel, and a display device are disclosed. The display panel includes a substrate layer; a light shielding metal layer and a first electrode plate of a storage capacitor on the substrate layer; a buffer layer covering the light shielding metal layer and the first electrode plate on the substrate layer; an active layer and a second electrode plate of the storage capacitor on the buffer layer; a gate insulating layer on the buffer layer and the active layer, and a source, a gate and a drain on the gate insulating layer.