Display Panel Asymmetric Voltage Timing for Charging Balance

The patent applies asymmetry by setting different voltage conversion timing for positive and negative data voltages. Specifically, the voltage conversion edge for negative data voltage is delayed relative to the data charging stage start time by a second target duration, while the voltage conversion edge for positive data voltage is delayed by a first target duration, where the second target duration is greater than the first target duration. This asymmetric timing compensation balances the charging rates of positive and negative sub-pixels, resolving the display quality issues caused by charging rate differences.

The patent applies preliminary action by performing voltage conversion in advance of the data charging stage, but with controlled timing offsets. The voltage conversion edge is positioned before the data charging stage starts, with the first target duration and second target duration ensuring that the conversion completes sufficiently early to allow proper charging while maintaining gray scale accuracy. This prevents line residual images while preserving display quality.

The patent applies local quality by introducing different timing parameters specifically for negative data voltage conversion while maintaining standard timing for positive data voltage. The second target duration (for negative voltage) is set greater than the first target duration (for positive voltage), providing localized compensation where needed. This approach balances charging rates without unnecessarily complicating the entire timing control system, as the asymmetry is applied only where required.