Display Panel Shift-Register Layout for Narrower Bezels
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Solution Overview
Problem
Display panels have wide bezels, which detract from their aesthetic appeal and functional integration in modern devices.
Innovation Solution
A display panel design that includes shift registers between adjacent pixel circuit groups, with specific sub-circuits and connections for clock and data lines, allowing for a non-overlapping layout that narrows the bezel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If shift registers are placed between pixel circuit groups, then the bezel width is reduced, but the layout complexity increases
Solution Approach 1:
The patent utilizes the column direction (vertical dimension) to route clock signal lines through clock connection lines, separating them from data lines that extend in the row direction. This dimensional separation allows shift registers to be positioned between pixel circuit groups without increasing horizontal bezel width, while managing routing complexity through structured multi-layer connections.
Solution Approach 2:
The gate drive circuit is segmented into multiple shift registers distributed between pixel circuit groups, with each shift register handling specific clock signal routing. This segmentation allows the display region to be divided into manageable sections, enabling compact integration without requiring a large continuous bezel area.
2Reliability
If clock signal lines are separated from data lines, then signal interference is reduced, but the number of connection lines increases
Solution Approach 1:
Clock signal lines are routed through clock connection lines that extend in the column direction, while data lines extend in the row direction. This orthogonal arrangement in different dimensions spatially separates the signal paths, minimizing electromagnetic interference without requiring additional horizontal space that would increase bezel width.
Solution Approach 2:
The clock connection lines serve multiple functions: they transport clock signals to shift registers, provide structural organization for the gate drive circuit, and enable the compact integration of timing control throughout the display region. This multi-functionality reduces the need for separate dedicated routing structures.
Data Source
AI summary
The present disclosure provides a display device and a display panel. The display panel includes: multiple pixel circuit rows at a side of the substrate, where multiple pixel circuit rows form multiple pixel circuit groups distributed in a column direction, and each pixel circuit group includes at least one pixel circuit row; a gate drive circuit, including multiple shift registers, where at least one shift register is between two adjacent pixel circuit groups. Each of the shift register includes: an output sub-circuit, connected with a first node and a second node, configured to perform output based on potentials of the first node and the second node; and an input sub-circuit, connected with multiple clock signal lines to control the potentials of the first node and the second node based on potentials of multiple clock signal lines.