Display Panel Bezel Width Reduction via 3D Component Stacking
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Solution Overview
Problem
Display panels with special-shaped outlines, such as circular or bang-shaped screens, face challenges in achieving narrow bezels due to uneven pixel distribution and parasitic capacitance, which affects display uniformity and requires larger compensation circuits, thereby limiting the bezel width.
Innovation Solution
The display panel design includes a compensation circuit with portions in different areas of the non-display region, rearranging electrical components to minimize bezel width by using part of the area saved from removing the test circuit to accommodate the compensation circuits, and optimizing the layout of power supply lines and shift registers to reduce bezel width.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a compensation circuit is added to compensate for parasitic capacitance in special-shaped displays, then display uniformity is improved, but the bezel width increases due to the larger area required for the compensation circuit
Solution Approach 1:
The patent transitions from planar arrangement to three-dimensional stacking by placing the compensation circuit, shift register, and other electrical components on different layers (first substrate and second substrate). This vertical integration allows the non-display area to be significantly reduced while maintaining all necessary functional components, thereby reducing bezel width without compromising display uniformity compensation capability
Solution Approach 2:
The patent implements nested arrangement where the compensation circuit is positioned in the first non-display area, the shift register is positioned in the second non-display area, and additional components are arranged in overlapping or nested configurations across multiple layers. This nesting strategy maximizes space utilization and minimizes the overall non-display area, effectively reducing bezel width
2Reliability
If electrical components are arranged in the non-display area to compensate for parasitic capacitance, then pixel performance is improved, but the non-display area increases
Solution Approach 1:
The patent utilizes multi-layer substrate structure where electrical components (compensation circuit, shift register, power supply lines) are distributed across different vertical layers. This three-dimensional arrangement reduces the horizontal footprint of the non-display area while ensuring all pixels receive adequate compensation for parasitic capacitance, thereby improving pixel performance without significantly increasing non-display area
Solution Approach 2:
The patent implements localized compensation strategies where compensation circuits are specifically positioned in regions with different pixel densities. In circular displays, the compensation circuit arrangement is optimized for the specific geometric characteristics, providing targeted compensation where needed most while minimizing the overall non-display area required
Data Source
AI summary
Embodiments of the present disclosure provide a display panel, a display device including the display panel and a method for fabricating the display panel. The display panel comprises a display area and a non-display area surrounding the display area. The display panel includes a pixel array, an edge of which defines a boundary between the display area and the non-display area, wherein the non-display area includes a first area and a second area arranged in sequence in a direction away from the pixel array; a compensation circuit configured to compensate for a parasitic capacitance of pixel in the pixel array, and including a first portion located in the first area and a second portion located in the second area; and a first shift register located in the second area. The second portion of the compensation circuit is aligned with the first shift register circuit in a circumferential direction of the pixel array.