Display Panel Bias Adjustment for Flicker Prevention

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Solution Overview

Problem

Display panels experience abnormal brightness and screen flickering when switched from high to low refresh rates due to ion polarization and threshold voltage shifts in driving transistors, affecting visual experience.

Innovation Solution

Implementing multiple bias adjustment stages with gradually changing bias adjustment signals to adjust the drain potential of driving transistors, reducing ion polarization and stabilizing the threshold voltage, thereby preventing abnormal brightness and flickering.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If the display panel is directly switched from a high refresh rate to a low refresh rate, then power consumption is reduced, but screen flickering and abnormal brightness occur

Engineering Contradiction:
Improvepower consumptionVSAvoiddisplay stability
Core Design Contradiction:
Loss of energyVSReliability

Solution Approach 1:

The patent applies preliminary action by performing bias adjustment on the driving transistor before the actual refresh rate switch takes effect. The bias adjustment stage is inserted between the high refresh rate mode and low refresh rate mode to pre-adjust the transistor parameters, preventing ion polarization and threshold voltage shifts that would otherwise cause screen flickering during the transition.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent segments the refresh rate transition process into distinct stages: a data writing stage followed by a bias adjustment stage. This segmentation allows the system to separately handle data display operations and transistor parameter adjustments, ensuring that the bias adjustment occurs without interfering with the normal display refresh cycle.

Inventive Principle:
Principle #1Segmentation

2Stability of the object's composition

If multiple bias adjustment stages are implemented, then threshold voltage stability is improved, but circuit complexity increases

Engineering Contradiction:
Improvethreshold voltage stabilityVSAvoidcircuit complexity
Core Design Contradiction:
Stability of the object's compositionVSDevice complexity

Solution Approach 1:

The patent merges the bias adjustment function with the existing data writing circuitry. The same transistor and capacitor structures used for data writing are reused for bias adjustment purposes, eliminating the need for separate dedicated bias adjustment components and reducing overall circuit complexity while still achieving threshold voltage stability.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent implements multi-functionality by designing the data writing transistor and storage capacitor to serve dual purposes: both data writing operations and bias adjustment operations. This universal design allows a single circuit structure to perform multiple functions, avoiding the need for additional dedicated bias adjustment circuits.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11922878B2Display panel and display device
Publication Date: 2024.03.05 XIAMEN TIANMA DISPLAY TECH CO LTD
  • US11922878B2 patent drawing
  • US11922878B2 patent drawing
  • US11922878B2 patent drawing

AI summary

A display panel includes: a pixel circuit, and a light-emitting element, that the pixel circuit includes a driving transistor configured to provide a driving current for the light-emitting element; a working process of the pixel circuit includes a data writing stage, in which a gate of the driving transistor receives a data signal, and a bias adjustment stage, in which a source or drain of the driving transistor receives a bias adjustment signal; and the pixel circuit has a frame refresh frequency F1, and a data refresh frequency including a first data refresh frequency F11 and a second data refresh frequency F22, that at least one second data refresh period includes N11 bias adjustment stages, a bias adjustment signal V11 is inputted in a first bias adjustment stage, and a bias adjustment signal Vi is inputted in an i-th bias adjustment stage, where V11≠Vi.