Display Panel Bias-Gate Compensation for Low-Frequency Mura
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Solution Overview
Problem
Display devices experience mura due to leakage currents and hysteresis characteristics of driving transistors, leading to luminance variations and pixel row interference during low driving frequencies, especially when data voltage changes rapidly.
Innovation Solution
A display device with a driving controller that compensates for data voltage differences between sub-pixels using a bias gate signal, adjusting the data voltage based on capacitance and grayscale differences, and applying compensation voltages to minimize luminance discrepancies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If the display device is driven at a low driving frequency, then power consumption is reduced, but luminance uniformity deteriorates due to leakage current and hysteresis characteristics
Solution Approach 1:
The patent applies preliminary action by writing compensation data voltage to pixel rows during the blank period before the active period begins. This pre-compensation approach addresses the anticipated luminance uniformity issues that would arise during low-frequency operation, allowing the display to maintain uniformity without requiring higher driving frequencies that would increase power consumption.
Solution Approach 2:
The patent implements local quality by applying different compensation voltages to different pixel rows based on their specific characteristics and position. The compensation data voltage is determined individually for each pixel row, allowing targeted correction of leakage current and hysteresis effects in specific regions while maintaining overall power efficiency at low driving frequencies.
2Speed
If data voltage changes rapidly to improve response time, then image update speed is improved, but mura occurs in other pixel rows due to interference through shared data lines
Solution Approach 1:
The patent uses compensation data voltage as an intermediary to mediate between the need for rapid data voltage changes and the prevention of mura interference. By introducing this intermediate compensation signal that accounts for the impact on adjacent pixel rows, the system can achieve fast image updates while preventing the harmful interference that would otherwise occur through shared data lines.
Solution Approach 2:
The patent applies preliminary anti-action by pre-calculating and writing compensation data voltage to pixel rows that will be affected by rapid data voltage changes in adjacent rows. This compensatory action is taken in advance during the blank period, counteracting the potential mura effects before they can manifest, thereby enabling rapid image updates without generating harmful interference.
3Stability of the object's composition
If bias voltage is supplied to improve luminance uniformity, then luminance consistency is improved, but device complexity increases due to additional control circuits
Solution Approach 1:
The patent merges the compensation function with the existing data writing operation by integrating the compensation data voltage into the normal data writing process. Rather than adding a completely separate bias voltage control system, the compensation is combined with the existing data line infrastructure, reducing the need for additional control circuits while maintaining luminance consistency.
Solution Approach 2:
The patent applies universality by making the data line serve multiple functions: it carries both the normal image data voltage and the compensation data voltage. This multi-functionality eliminates the need for dedicated bias voltage lines and control circuits, reducing device complexity while still achieving improved luminance consistency through the compensation mechanism.
Data Source
AI summary
A display device includes a display panel including a display area including sub-pixels, a data driver providing a data voltage to each of the sub-pixels through a data line, a gate driver providing a bias gate signal to each of the sub-pixels and a driving controller compensating for the data voltage written in a second area to which the bias gate signal having an activation level in a first period in which the data voltage is written in the first area is applied based on a first data voltage corresponding to a grayscale of a first area of the display area and a second data voltage corresponding to a grayscale of a different area from the first area of the display area.