Display Panel IC Bonding Structure for Moisture-Resistant Adhesion

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Solution Overview

Problem

In OLED display technologies, the poor adhesive force between barrier layers and organic material film layers in the IC bonding area leads to issues such as water absorption and thermal expansion, causing the barrier and metal layers to peel off during reliability tests.

Innovation Solution

A display panel structure is introduced, where a first passivation layer covers the peripheral area of a pin in the IC bonding portion, and a first barrier layer and a first metal layer are formed to improve adhesive forces and prevent water absorption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If a barrier layer is formed on the organic material film layer in the IC bonding area, then water absorption is prevented, but the adhesive force between layers is poor causing peeling

Engineering Contradiction:
Improvewater absorptionVSAvoidadhesive force
Core Design Contradiction:
Object-affected harmful factorsVSStrength

Solution Approach 1:

The patent divides the protective layering structure into multiple distinct layers: organic material film layer, barrier layer, and planarization layer, each performing specific functions. The barrier layer is segmented to cover only necessary areas while the planarization layer provides overall protection, preventing water absorption without compromising adhesive strength.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The planarization layer acts as an intermediary between the barrier layer and the IC bonding area, improving adhesion while the barrier layer provides water protection. This mediator layer resolves the contradiction by providing a bonding interface that prevents peeling while allowing the barrier layer to fulfill its water prevention function.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Object-affected harmful factors

If the barrier layer and metal layer are stacked in the IC bonding area, then water absorption is reduced, but thermal expansion causes peeling during reliability tests

Engineering Contradiction:
Improvewater absorptionVSAvoidreliability under high temperature and humidity
Core Design Contradiction:
Object-affected harmful factorsVSReliability

Solution Approach 1:

The patent modifies the structural parameters of the layering system by adjusting the thickness, material composition, and coverage area of each layer. The barrier layer is designed with specific thickness and positioning parameters that optimize both water protection and thermal expansion compatibility, preventing peeling during reliability tests while maintaining water absorption resistance.

Inventive Principle:
Principle #35Parameter changes

3Shape

If the IC bonding area is coated with planarization layer or pixel definition layer, then surface flatness is improved, but adhesive force between barrier layer and organic material film layer deteriorates

Engineering Contradiction:
Improvesurface flatnessVSAvoidadhesive force
Core Design Contradiction:
ShapeVSStrength

Solution Approach 1:

The patent applies different layer configurations to different areas: the barrier layer is positioned to cover the IC bonding area specifically, while the planarization layer provides surface flatness in the display area. This local differentiation allows each layer to optimize its function without compromising the adhesive strength in critical bonding regions.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS12336413B2Display panel, display device, and manufacturing method of display panel
Publication Date: 2025.06.17 CHENGDU BOE OPTOELECTRONICS TECH CO LTD
  • US12336413B2 patent drawing
  • US12336413B2 patent drawing
  • US12336413B2 patent drawing

AI summary

The present disclosure relates to a display panel, a display device and a manufacturing method of a display panel. The display panel includes: a display substrate having a display area and a non-display area, the display substrate including a substrate and an IC bonding portion which includes: a pin; a first passivation layer located on one side of the substrate adjacent to the pin and covering a peripheral area of the pin, and exposing a central area of the pin; a first barrier layer located on one side of the first passivation layer away from the substrate and covered at the first passivation layer and an edge of the first passivation layer connected to the pin; and a first metal layer located on one side of the first barrier layer away from the substrate, at least covering a central portion of the pin, and electrically connected to the pin.