Display Panel Bonding-Pin Layout for Flexible-Circuit Alignment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In chip-on-glass and chip-on-film display apparatuses, the alignment precision between flexible printed circuits and signal lines is challenging, leading to potential shorts due to thermal expansion and misalignment, particularly in regions far from the virtual central line.
Innovation Solution
The display panel incorporates connecting portions between signal lines and bonding pins, arranged in specific angles and configurations to facilitate precise alignment of circuit pins with bonding pins, minimizing overlap and reducing the risk of shorts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If flexible printed circuit is directly mounted on display panel edge using anisotropic conductive film, then bonding is achieved, but alignment precision deteriorates leading to potential shorts due to thermal expansion and misalignment
Solution Approach 1:
The patent introduces bonding pins as an intermediary component between the flexible printed circuit and the display panel substrate. These bonding pins serve as precise alignment references that mediate the connection, ensuring accurate electrical contact while preventing misalignment and shorts caused by direct mounting using anisotropic conductive film.
Solution Approach 2:
The bonding pins are pre-formed on the display panel substrate with predetermined positions and orientations before the flexible printed circuit is mounted. This preliminary positioning establishes precise alignment references in advance, preventing alignment issues during the bonding process and under thermal expansion conditions.
2Ease of manufacture
If bonding pins are arranged parallel to signal lines, then manufacturing is simplified, but alignment precision deteriorates in regions far from virtual central line
Solution Approach 1:
The patent employs asymmetric arrangement of bonding pins relative to the signal lines. Instead of parallel alignment, the bonding pins are positioned at specific angled orientations that compensate for thermal expansion effects and maintain precise alignment across the entire display panel, including regions far from the virtual central line.
Solution Approach 2:
The bonding pins are positioned with different local orientations and spacings depending on their location on the display panel. Regions far from the virtual central line have bonding pins arranged with specific angular offsets to compensate for greater thermal expansion effects, while central regions use different positioning, optimizing alignment precision locally throughout the panel.
3Object-affected harmful factors
If bonding pins are positioned far from signal lines, then short risk is reduced, but electrical connection reliability deteriorates
Solution Approach 1:
The patent positions bonding pins at angled orientations relative to the signal lines rather than directly adjacent to them. This dimensional change in positioning creates sufficient spacing to reduce short risk while the angled configuration maintains effective electrical connection by optimizing the bonding interface geometry and contact area.
Data Source
AI summary
A display panel having a bonding region for bonding a flexible printed circuit in a peripheral region is provided. The display panel includes a plurality of first signal lines on a base substrate; and a plurality of bonding pins on the base substrate and in the bonding region. The plurality of bonding pins include a plurality of first bonding pins respectively electrically connected to the plurality of first signal lines. The display panel further includes a plurality of connecting portions respectively connecting the plurality of first signal line portions to the plurality of first bonding pin portions. The respective first bonding pin portion includes a first sub-layer, a second sub-layer, and a third sub-layer, stacked together. The respective connecting portion is in a same layer as one of the first sub-layer, a second sub-layer, and a third sub-layer.


