Display Panel Bonding Test Region Sealant Segmentation
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Solution Overview
Problem
Large-scaled display panels face issues with exposed test pads in the bonding test region, leading to static electricity introduction and electrostatic breakdown, which lowers display panel performance.
Innovation Solution
The display panel is designed with a bonding test region divided into sealant-blanked and sealant-coated sub regions, where test terminals are sealed in the coated sub regions, and a flattening insulation layer covers the test terminals, preventing exposure and static electricity ingress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a two-part coating method is used to seal test terminals from both ends to the middle of the bonding test region, then production efficiency is improved, but test pads in the middle become exposed, leading to electrostatic breakdown and performance degradation
Solution Approach 1:
The bonding test region is segmented into a first bonding test subregion and a second bonding test subregion, with sealant applied in two separate parts from opposite ends. Each part seals test terminals in its respective subregion, ensuring complete coverage without overlap while maintaining electrostatic protection across the entire region.
Solution Approach 2:
The sealing approach transitions from a single-direction linear progression to a two-directional simultaneous approach, applying sealant from both ends of the bonding test region toward the middle. This dimensional change in the coating process enables complete coverage of test terminals while preventing the exposure problem that occurs with single-direction sealing.
2Manufacturing precision
If spacing is deployed between glue coating areas to prevent overlap, then sealant height control is improved, but test pads in the blank region become exposed, causing electrostatic breakdown
Solution Approach 1:
The bonding test region is divided into two distinct subregions with separate sealant coating operations. The first sealant coating seals test terminals in the first subregion, and the second sealant coating seals test terminals in the second subregion, ensuring all test terminals are covered without requiring a blank spacing region.
Solution Approach 2:
The sealing process transitions from single-direction linear progression to two-directional simultaneous approach, applying sealant from both ends toward the middle. This enables complete coverage of test terminals while maintaining precise control over sealant height through controlled overlap or meeting at the center line.
3Reliability
If the bonding test region is completely sealed with sealant, then electrostatic protection is improved, but sealant height may exceed polarizer height, affecting display panel function
Solution Approach 1:
The bonding test region is segmented into two subregions with separate sealant coating operations. By controlling each sealant application to target specific subregions and monitoring the meeting point at the center line, the sealant height is maintained within acceptable limits while ensuring complete electrostatic protection of all test terminals.
Solution Approach 2:
Different sealing strategies are applied to different subregions of the bonding test region. The first sealant coating targets the first bonding test subregion, and the second sealant coating targets the second bonding test subregion, allowing localized control over sealant height and coverage to prevent excessive height while ensuring complete protection.
Data Source
AI summary
The present application provides a display panel. The display panel includes a display region and a bonding test region. The display panel includes a base substrate which is provided with a plurality of first test terminals. The bonding test region includes a sealant-blanked sub region and sealant-coated sub regions. Each of the first test terminals is located in the sealant-coated sub region, and the base substrate and each of the first test terminals are provided with a sealing glue layer covering each of the first test terminals.