Display Panel Pixel Circuit Layout for Lower Crosstalk
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Solution Overview
Problem
Existing display panels, such as OLED panels, face challenges in optimizing the arrangement and connectivity of pixel driving circuits and light-emitting devices to enhance display performance and efficiency.
Innovation Solution
The display panel incorporates a novel arrangement of pixel driving circuits with capacitors, driving transistors, and data writing transistors, featuring staggered through holes in insulating layers and distinct coupling positions for electrode plates, allowing for improved connectivity and alignment of semiconductor segments, thereby optimizing the display panel's structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the pixel driving circuits and light-emitting devices are arranged in a conventional configuration, then the structure is simple, but the signal transmission quality and electrical interference reduction are insufficient
Solution Approach 1:
The patent applies dimensionality change by transitioning from a planar arrangement to a three-dimensional stacked configuration. The first and second pixel driving circuits are arranged in different layers (first layer and second layer), with corresponding through holes staggered in the thickness direction. This vertical stacking approach improves signal transmission quality and reduces electrical interference while managing the increased structural complexity through systematic layering.
Solution Approach 2:
The patent implements nesting by placing the first pixel driving circuit and second pixel driving circuit within different layers of the display panel structure. The through holes in the insulating layers are staggered, creating a nested arrangement where components in one layer are positioned relative to components in another layer, optimizing space utilization and signal integrity.
2Object-affected harmful factors
If the through holes in insulating layers are aligned, then the manufacturing process is simpler, but the electrical interference between adjacent circuits increases
Solution Approach 1:
The patent applies asymmetry by deliberately staggering the positions of through holes in different insulating layers. The first through hole in the first insulating layer and the second through hole in the second insulating layer are not aligned but offset from each other in the thickness direction. This asymmetric arrangement reduces electrical interference between adjacent circuits while the manufacturing process maintains precision through controlled staggered positioning.
3Reliability
If the electrode plates are coupled at the same position, then the connection is more direct, but the electrical interference and crosstalk increase
Solution Approach 1:
The patent resolves the contradiction by utilizing the thickness direction (z-axis) to separate the coupling positions of electrode plates. The first electrode plate in the first pixel driving circuit couples to the first light-emitting device at a first position, while the first electrode plate in the second pixel driving circuit couples to the second light-emitting device at a second position that is staggered in the thickness direction. This vertical separation maintains connection stability while reducing crosstalk and electrical interference between adjacent circuits.
Data Source
AI summary
A display panel includes a first pixel driving circuit and a second pixel driving circuit. A data writing transistor and a driving transistor in the first pixel driving circuit, a driving transistor and a data writing transistor in the second pixel driving circuit are sequentially arranged. In the first pixel driving circuit, a first electrode plate of a capacitor is coupled to the driving transistor at a first coupling position and coupled to a first light-emitting device at a second coupling position located at a side of the first coupling position away from the data writing transistor. In the second pixel driving circuit, a first electrode plate of a capacitor is coupled to the driving transistor at a third coupling position and coupled to a second light-emitting device at a fourth coupling position located between the third coupling position and the data writing transistor.