Display Panel Peripheral Circuit Layout Optimization

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Solution Overview

Problem

Existing display panels face challenges in minimizing dead space and achieving high-quality images while efficiently arranging internal circuit units and connection lines to reduce the peripheral area, which affects the overall performance and design flexibility of display apparatuses.

Innovation Solution

The display panel incorporates a substrate with a display area and a peripheral area, featuring first and second internal circuit units arranged in opposite directions, connection lines that overlap a common voltage power source line, and a corner internal circuit unit providing distinct signals, allowing for efficient signal distribution and reduced dead space.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If internal circuit units are arranged in a single direction, then the layout is simple, but the peripheral area increases and dead space is not minimized

Engineering Contradiction:
Improvelayout complexityVSAvoidperipheral area
Core Design Contradiction:
Device complexityVSArea of stationary object

Solution Approach 1:

The internal circuit unit is divided into multiple sub-units (first internal circuit unit, second internal circuit unit, third internal circuit unit) that are arranged in different directions. This segmentation allows each sub-unit to be optimally positioned to reduce dead space while maintaining functional integrity of the overall circuit system.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different sub-units of the internal circuit are arranged asymmetrically in opposite directions relative to the display area. The first sub-unit extends in one direction while the second sub-unit extends in the opposite direction, creating an asymmetric layout that efficiently utilizes the peripheral area and minimizes dead space.

Inventive Principle:
Principle #4Asymmetry

2Reliability

If connection lines are arranged to avoid overlapping, then signal interference is minimized, but the peripheral area increases

Engineering Contradiction:
Improvesignal interferenceVSAvoidperipheral area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

Connection lines are allowed to overlap with the common voltage power source line in the peripheral area. This merging of spatial paths reduces the overall peripheral area required, while the functional separation maintains signal integrity and minimizes interference.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The connection lines utilize the vertical dimension by overlapping with power source lines in the planar view. This dimensional approach allows multiple signal paths to coexist in the same footprint area without causing interference, effectively reducing the peripheral area.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Area of stationary object

If the peripheral area is reduced, then dead space is minimized, but the arrangement of internal circuits and connection lines becomes more difficult

Engineering Contradiction:
Improveperipheral areaVSAvoidarrangement difficulty
Core Design Contradiction:
Area of stationary objectVSEase of manufacture

Solution Approach 1:

Different regions of the peripheral area are assigned different functions: some regions contain internal circuit sub-units arranged in specific directions, while other regions accommodate overlapping connection lines. This local differentiation allows efficient space utilization while maintaining manufacturing feasibility in each localized area.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20240324374A1Display panel
Publication Date: 2024.09.26 SAMSUNG DISPLAY CO LTD
  • US20240324374A1 patent drawing
  • US20240324374A1 patent drawing
  • US20240324374A1 patent drawing

AI summary

A display panel includes: a substrate comprising a display area and a peripheral area; first signal lines on the substrate extending in a first direction; data lines on the substrate extending in a second direction crossing the first direction; pixel circuits arranged in a matrix along the first direction and the second direction and display elements respectively connected to the pixel circuits, the pixel circuits and the display elements being arranged in the display area; a first internal circuit unit comprising first internal circuits arranged along the first direction in the peripheral area; connection lines in the peripheral area to connect each of the first internal circuits to each of the first signal lines; and a common voltage supply line in the peripheral area between the first internal circuit unit and an edge of the substrate, wherein at least some of the connection lines overlap the common voltage supply line.