Display Panel Clock Line Compensation for Signal Distortion
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Solution Overview
Problem
In liquid crystal display (LCD) apparatuses, the reduction of source driving chips leads to increased signal line lengths, causing signal distortion and resulting in horizontal line defects on the display screen due to the gate signals being affected by the outermost source driving chip.
Innovation Solution
The implementation of a display panel with a dual clock signal system where first and second clock lines have the same time constant, with dummy terminals and variable resistance elements to compensate for manufacturing errors, ensuring that gate signals are minimized and not distorted, thereby preventing horizontal line defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the number of source driving chips is decreased, then the manufacturing cost and device complexity are reduced, but the signal line length is increased causing signal distortion and horizontal line defects
Solution Approach 1:
The gate driving circuit is divided into multiple independent gate driving parts (first gate driving part and second gate driving part) that are distributed at different locations on the array substrate. This segmentation allows the long gate line to be driven from multiple points, reducing signal distortion while maintaining the reduced number of source driving chips.
Solution Approach 2:
Dummy terminals are introduced as intermediary elements connected to the clock lines. These dummy terminals have the same capacitance as the gate driving part capacitance, serving as compensatory elements that balance the time constants and prevent signal distortion caused by the reduced number of source driving chips.
2Device complexity
If the signal line length is increased to reduce source driving chips, then device complexity is reduced, but signal distortion occurs due to the outermost source driving chip affecting gate signals
Solution Approach 1:
The gate driving function is segmented into multiple independent gate driving parts positioned at different locations. This segmentation ensures that no single source driving chip needs to drive an excessively long gate line, thereby preventing signal distortion while maintaining reduced device complexity.
Solution Approach 2:
The design incorporates feedback through the dummy terminals that compensate for signal distortion. By matching the capacitance of dummy terminals to the gate driving part capacitance, the system creates a balanced feedback mechanism that corrects signal distortion caused by long signal lines.
3Ease of manufacture
If dummy terminals with different capacitance are used, then the clock signal transmission is simplified, but time constant differences cause gate signal distortion
Solution Approach 1:
The capacitance value of dummy terminals is specifically adjusted to match the capacitance of the gate driving part. This parameter change ensures that the time constants are equalized, preventing gate signal distortion while maintaining ease of manufacture through standardized capacitance values.
Data Source
AI summary
In a display panel and a display apparatus having the display panel, the display panel includes array and opposite substrates. The array substrate includes display and peripheral areas. Gate and source lines are formed in the display area. A gate driving part and first and second clock lines are formed in the peripheral area. The gate driving part outputs gate signals to the gate line. The first and second clock lines respectively transmit first and second clock signals to the gate driving part. The opposite substrate is combined with the array substrate and includes a common electrode layer. The common electrode layer has an opening portion patterned to expose the first and second clock lines. The exposed portions of the first and second clock lines have substantially the same area. Thus, delays of the gate signals may be minimized and distortion of the gate signals may be prevented.


