Display Panel Clock Frequency Control for Stable Pixel Output
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Solution Overview
Problem
Display panels experience unstable output signals due to leakage currents, leading to issues like uneven luminescence and flicker during grayscale switching, primarily caused by the effects of long-term clock signal stability and power consumption.
Innovation Solution
Implement a multi-stage holding stage in the data refresh period of the pixel circuit, where the clock pulse frequency transitions smoothly from a high frequency to lower frequencies, including a first frequency during data writing, a second frequency, and a third frequency in the holding stage, to stabilize the output signal and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the clock signal maintains a high frequency during the holding stage, then the output signal stability is improved, but the power consumption increases
Solution Approach 1:
The holding stage is divided into multiple sub-stages (first holding stage, second holding stage, third holding stage) with different clock frequencies. This segmentation allows the system to use high frequency only when needed for stability and lower frequency for power saving, resolving the contradiction between signal stability and power consumption.
Solution Approach 2:
The clock frequency is dynamically adjusted during different phases of the holding stage. The system transitions from high frequency during data writing to lower frequencies during holding stages, adapting the frequency to the operational requirements at each moment to balance stability and power consumption.
2Use of energy by moving object
If the clock signal frequency is reduced during the holding stage, then the power consumption is reduced, but the output signal stability deteriorates
Solution Approach 1:
The holding stage is segmented into multiple phases with different frequency requirements. The first holding stage uses a first frequency, the second holding stage uses a second frequency, and the third holding stage uses a third frequency. This segmentation allows the system to reduce frequency for power saving while maintaining stability through structured phase management.
Solution Approach 2:
The system employs periodic clock signals with varying frequencies during different holding stages. By using periodic action with adaptive frequencies, the system maintains signal stability through regular timing while reducing power consumption through lower frequency periods, resolving the contradiction between stability and energy efficiency.
3Device complexity
If the pixel circuit operates in a single holding stage, then the device complexity is reduced, but the signal stability and power efficiency are compromised
Solution Approach 1:
The holding stage is divided into multiple sub-stages (first, second, and third holding stages) with different clock frequencies. This segmentation improves signal stability and power efficiency by optimizing the clock signal characteristics for each specific phase, while the modular structure keeps the overall device complexity manageable through systematic organization.
Data Source
AI summary
A display panel includes a pixel circuit including a driving transistor, a driving circuit configured to provide a control signal to the pixel circuit, and a clock signal line configured to provide a clock signal for the driving circuit. A data refresh period of the pixel circuit includes a data writing stage and a holding stage. When the pixel circuit is operated in the data writing stage, a clock pulse frequency of the clock signal is a first frequency F1 in at least one stage of the N stages. When the pixel circuit is operated in the holding stage, the clock pulse frequency of the clock signal is a second frequency F2 in at least one stage of the N stages, the clock pulse frequency of the clock signal is a third frequency F3 in at least one stage of the N stages. F1>F2>F3≥0.