Display Panel Clock Modulation for Mixed-Speed Gate Driving
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Solution Overview
Problem
Existing organic light-emitting display devices face challenges in reducing power consumption while maintaining high luminous efficiency and flexibility.
Innovation Solution
A display panel is divided into high-speed and low-speed driving areas, with a gate driver supplying gate signals and a drive IC managing data voltages, and a clock signal modulated to maintain previous data voltages in the low-speed area, reducing power consumption by minimizing data voltage application.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the display area is driven at a high frequency to improve response speed and image quality, then the image quality and response speed are improved, but the power consumption increases
Solution Approach 1:
The display area is divided into a first area and a second area, with different driving frequencies applied to each region. The first area is driven at a first frequency while the second area is driven at a second frequency, allowing the system to optimize for both speed and power consumption by segmenting the display into zones with different performance requirements
Solution Approach 2:
Different regions of the display are assigned different driving characteristics - the first area receives higher frequency signals for better response speed, while the second area uses lower frequency signals to reduce power consumption. This local differentiation allows each region to operate at its optimal performance point
2Reliability
If data voltage is continuously applied to maintain image quality, then the image quality is maintained, but the power consumption increases
Solution Approach 1:
The clock signal is configured with asymmetric high and low intervals, creating a periodic pattern where data voltage is applied during the high interval and maintained without continuous application during the low interval. This periodic action allows the capacitor to hold the charge, maintaining image quality while reducing continuous power consumption
Solution Approach 2:
Data voltage is applied in advance during the high interval of the clock signal to charge the capacitor, preparing the pixel for the subsequent low interval where no data voltage is applied. This preliminary charging action ensures image quality is maintained during the power-saving period without requiring continuous voltage application
Data Source
AI summary
A display panel and a display device including the same are discussed. The display panel includes a display area in which a plurality of data lines, a plurality of gate lines, and a plurality of sub-pixels are disposed, and a gate driver configured to supply gate signals to the gate lines. The display area includes a high-speed driving area, and a low-speed driving area driven at a frequency lower than that of the high-speed driving area. One cycle of a clock signal input to the gate driver includes a high interval with a gate high voltage and a low interval with a gate low voltage. A high interval of the clock signal is longer than a high interval of the high-speed driving area at a scanning time point of a first pixel line from which scanning of the low-speed driving area is started.