Display Panel Clock Signal Routing for Narrow Bezel
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Solution Overview
Problem
High-resolution liquid crystal displays (LCDs) require numerous clock signals, leading to resistance and capacitance differences between clock lines, which can cause horizontal line defects, and existing routing designs to reduce these differences increase the bezel width, hindering the development of narrow bezel displays.
Innovation Solution
A display panel design with a non-display area including a gate driver on array (GOA) unit, routing area, and wiring area, where clock signal traces are arranged in a specific direction, and clock signal transfer lines are bent and overlapped with a dataline black matrix less (DBS) common electrode trace to reduce resistance differences and bezel width.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the CK line routing design is configured to reduce the resistance difference, then the resistance difference between clock signal traces is reduced, but the width of the bezel increases
Solution Approach 1:
The patent introduces a routing area arranged in the second direction (vertical to the first direction), allowing clock signal transfer lines to extend vertically through this dedicated routing zone. This dimensional change enables the transfer lines to bypass horizontal routing constraints, reducing resistance differences while maintaining compact horizontal bezel width. The routing area serves as a vertical corridor for signal transmission, separating routing functions from display area constraints.
Solution Approach 2:
The non-display area is segmented into distinct functional zones: a routing area for vertical signal transmission and a first wiring area for horizontal clock signal trace arrangement. This segmentation allows clock signal transfer lines to utilize the routing area for low-resistance vertical connections to the GOA unit, while clock signal traces in the wiring area handle horizontal distribution. The spatial division enables optimized signal paths without increasing overall bezel width.
2Measurement precision
If more clock signal traces are arranged to support higher resolution, then the resolution capability is improved, but the resistance and capacitance differences between lines increase causing horizontal line defects
Solution Approach 1:
The patent implements different routing strategies for different segments of the clock signal distribution network. Clock signal transfer lines in the routing area use vertical paths with controlled lengths and routing configurations tailored to their specific positions. Each transfer line's routing is locally optimized based on its distance from the GOA unit and its position in the array, ensuring uniform signal characteristics across all clock lines despite varying path lengths. This local optimization prevents horizontal line defects while supporting high resolution.
Data Source
AI summary
The application discloses a display panel. The display panel includes: a dataline black matrix less (DBS) common electrode trace arranged in a routing area; a plurality of clock signal traces arranged in a first wiring area along a first direction; and a plurality of clock signal transfer lines connected to the plurality of clock signal traces in a one-to-one correspondence, wherein each of the clock signal transfer lines passes through the routing area and extends to a gate driver on array (GOA) unit area along the first direction, and at least one of the clock signal transfer lines is bent and arranged in the routing area.