Display Panel Gate Driver Segmentation for Stable Clock Signals
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Solution Overview
Problem
Existing display technologies face challenges in reducing the load on clock signal lines, particularly in large-sized display panels, leading to instability in signal output and affecting display quality.
Innovation Solution
The display panel design divides shift register units into multiple groups, each corresponding to separate clock signal line groups, reducing the number of units connected to each line and using connection lines to distribute clock signals efficiently, thereby lowering the load on individual clock signal lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If multiple shift register units are connected to a single clock signal line, then device complexity is reduced, but signal output stability deteriorates due to increased load
Solution Approach 1:
The patent divides the shift register units into multiple groups (first group and second group), with each group connected to separate clock signal lines (first clock signal line and second clock signal line). This segmentation reduces the number of units connected to each clock signal line, thereby reducing the load on each line and stabilizing signal output while maintaining manageable device complexity through organized grouping.
2Reliability
If shift register units are divided into multiple groups with separate clock signal lines, then signal output stability is improved, but device complexity increases
Solution Approach 1:
The patent extracts the clock signal distribution function by separating shift register units into distinct groups that receive clock signals from different clock signal lines. This extraction allows each clock signal line to serve a smaller, dedicated group of units, reducing individual line load and improving signal stability, while the systematic grouping prevents excessive overall complexity.
3Productivity
If more shift register units are connected to each clock signal line, then productivity is improved by reducing the number of clock signal lines, but signal output stability deteriorates
Solution Approach 1:
The patent segments shift register units into multiple groups, each served by dedicated clock signal lines. This segmentation optimizes the balance between productivity and reliability by ensuring each clock signal line drives a manageable number of units, preventing signal degradation while maintaining efficient overall system operation through organized modular groups.
Data Source
AI summary
A display panel, a driving method, and a display device. The display panel includes: a base substrate, subpixels, driving lines, data lines, a gate driving circuit including clock signal lines and shift register units arranged in extension direction of clock signal lines. The clock signal lines is divided into clock signal line groups; the shift register units is divided into register unit groups; the shift register units in same register unit group are cascaded, adjacent two of shift register units in the extension direction are in different register unit groups; one register unit group corresponds to one clock signal line group; the gate of an input transistor is connected to a clock signal line in a corresponding clock signal line group, the second pole of input transistor is connected to the gate of an output transistor; the second pole of output transistor is connected to at least one driving line.