Display Panel Clock Signal Line Groups for Image Sticking
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Solution Overview
Problem
Active-matrix organic light emitting diode (AMOLED) display panels face issues with image sticking and uneven display due to reduced charging time, which occurs when the refresh rate is low or the number of memories is reduced to cut costs, leading to insufficient data voltage writing.
Innovation Solution
The display panel design includes clock signal line groups with sequentially delayed pulses, overlapping gate control signals across adjacent rows, and a time division multiplexing circuit to increase the duration for writing data voltage, ensuring sufficient data voltage writing and reducing image sticking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the refresh rate is reduced or the number of memories is reduced to cut costs, then the power consumption is reduced and cost is reduced, but the charging time is insufficient leading to image sticking and uneven display
Solution Approach 1:
The patent implements a dual-clock signal system where even-row pixels are driven by a first clock signal and odd-row pixels are driven by a second clock signal. This periodic alternation allows different rows to be charged in different time periods, effectively extending the overall charging time for the entire display panel without increasing the refresh rate. The gate drive circuit outputs scanning signals in an interlaced manner, with even rows scanned first followed by odd rows, ensuring sufficient charging time for each row while maintaining power efficiency.
2Quantity of substance
If the number of memories is reduced to cut costs, then the cost is reduced, but the charging time is reduced leading to insufficient data voltage writing
Solution Approach 1:
The patent divides the display panel into two separate groups: even-row pixels and odd-row pixels. Each group is driven by its own dedicated clock signal and scanned by its own gate drive circuit. This segmentation allows the charging process to be distributed across different time periods, with even rows charged during one period and odd rows charged during another period. This effectively doubles the available charging time without requiring additional memory units, thus reducing cost while maintaining sufficient charging duration for data voltage writing.
3Productivity
If the refresh rate is low, then the power consumption is reduced, but the charging time per frame is reduced leading to image sticking
Solution Approach 1:
The patent implements continuous charging across frame boundaries by maintaining the dual-clock signal system operating continuously. Even when the refresh rate is low, the even-row and odd-row charging cycles continue without interruption, with each row group receiving its designated charging time. This continuous operation ensures that data voltage writing is always sufficient regardless of the refresh rate, preventing image sticking while allowing the system to operate at lower power consumption levels.
Data Source
AI summary
The present disclosure discloses a display panel. The display panel includes clock signal line groups and gate drive circuits. Each clock signal line group includes a first clock signal line and a second clock signal line, and each gate drive circuit includes shift register units cascade-connected in sequence.