Display Panel Clock Signal Parasitic Capacitance Stabilization
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Solution Overview
Problem
Existing OLED display devices face technical issues due to grooves above clock lines being offset, leading to excessive changes in parasitic capacitances, which affects signal output and display performance.
Innovation Solution
A display panel design that includes a low-potential signal line with through holes arranged in an array to form repeating units, ensuring equal overlapping areas for clock signal lines and through holes, thereby stabilizing parasitic capacitances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If grooves are dug in the metal of anode layer above clock signal lines to release water vapor, then water vapor release is improved, but mask alignment deviation causes groove offset leading to excessive parasitic capacitance changes
Solution Approach 1:
The patent extracts the water vapor release function from the groove structure and relocates it to the organic layer above the pixel electrode. By digging grooves in the organic layer instead of the metal anode layer, the water vapor release function is maintained while eliminating the alignment sensitivity issue. The grooves are positioned at specific locations above the pixel electrode where they can effectively release water vapor without interfering with clock signal lines.
Solution Approach 2:
The patent introduces the organic layer as an intermediary structure between the pixel electrode and the metal anode. Instead of directly creating grooves in the metal anode layer, the organic layer serves as a mediator that can be etched to create grooves for water vapor release. This intermediary approach decouples the water vapor release function from the metal layer alignment requirements.
2Ease of manufacture
If grooves are offset relative to clock lines due to mask alignment deviation, then manufacturing process is simplified, but parasitic capacitances between clock lines and anode metal change excessively
Solution Approach 1:
The patent extracts the water vapor release function from the groove structure and relocates it to the organic layer above the pixel electrode. By digging grooves in the organic layer instead of the metal anode layer, the water vapor release function is maintained while eliminating the alignment sensitivity issue. The grooves are positioned at specific locations above the pixel electrode where they can effectively release water vapor without interfering with clock signal lines.
Solution Approach 2:
The patent applies local quality by positioning grooves at specific locations above the pixel electrode rather than uniformly across the anode layer. The grooves are strategically placed to target water vapor release areas while avoiding critical alignment zones with clock signal lines. This localized approach allows the trenches to serve their primary function of water vapor release without creating parasitic capacitance issues with the clock lines.
3Reliability
If equal overlapping area is maintained between clock signal lines and through holes, then parasitic capacitance stability is improved, but design complexity increases
Solution Approach 1:
The patent makes the through holes serve multiple functions: they act as both electrical connections (vertical interconnects) and as alignment references for maintaining equal overlapping areas with clock signal lines. By designing the through hole array to inherently provide equal overlapping areas, the structure simultaneously achieves electrical connectivity and parasitic capacitance control without requiring additional adjustment mechanisms.
Data Source
AI summary
The present disclosure provides display panels and display devices. In the display panel, the through holes are designed, so that when the position of the through holes is offset, an overlapping area of any clock signal line and the through holes remains unchanged, and the overlapping area of each clock signal line and the through holes is the same, so that the parasitic capacitance of each clock signal line is similar or even equal, avoiding different signal delays of adjacent clock signal lines, and avoiding signal delay changes caused by impedance changes of the clock signal lines, so that the display panel can display normally.